3.1.23 Voltage Swell Threshold
For each half-cycle of the dominant phase, the RMS values of all voltages are calculated, taking into account both the fundamental and harmonic components. Each calculated value is then compared to the corresponding SWELL_THRESHOLD_Vx, (where x = [A, B, C]), to assess whether a voltage swell condition is present. For each half cycle that a voltage swell exists, the associated flag, SWELL_DET_Vx is set to 1.
A threshold is allowed for each phase and is computed using the native phase voltages before transformation to implied 4WY service. This allows setting different thresholds for non-balanced service types.
The SWELL_THRESHOLD_Vx is stored in the uQ0.32 format, therefore, set the threshold value as follows:
| Name: | SWELL_THRESHOLD_Vx |
| Property: | Read-Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SWELL_THRESHOLD_Vx[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SWELL_THRESHOLD_Vx[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SWELL_THRESHOLD_Vx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWELL_THRESHOLD_Vx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |