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Libero IDE v9.x
Libero IDE v9.x
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  2. 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  3. 1.2 Analog System Builder (ASB)
  4. 1.2.8 ASB Advanced Options – Calibration
  5. 1.2.8.5 Calibration Side Effects
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  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
    • 1 Introduction
    • 1.1 FlashROM
    • 1.2 Analog System Builder (ASB)
      • 1.2.1 Analog System Builder Reference
      • 1.2.2 ASB Port List
      • 1.2.3 Analog System Builder Main Window
      • 1.2.4 Modify Sampling Sequence
      • 1.2.5 External Trigger Signals in Analog System Builder
      • 1.2.6 Analog System Builder Output Files
      • 1.2.7 ASB Advanced Options
      • 1.2.8 ASB Advanced Options – Calibration
        • 1.2.8.1 How Does Calibration in the ASB Work?
        • 1.2.8.2 Voltage Reference
        • 1.2.8.3 Saturation
        • 1.2.8.4 How Does Calibration Affect Simulations?
        • 1.2.8.5 Calibration Side Effects
      • 1.2.9 ASB Connectivity and Calibration
      • 1.2.10 Analog System Builder Calibration Output Files
      • 1.2.11 ASB Advanced Options - ASSC RAM
      • 1.2.12 ASB Advanced Options - SMEV RAM
      • 1.2.13 ASB Advanced Options - SMEV Status
      • 1.2.14 ASB Advanced Options - ADC Results
      • 1.2.15 ASB Advanced Options - ADC Status
      • 1.2.16 ASB Advanced Options - ACM Bus
      • 1.2.17 ASB Advanced Options - ACM Clock
      • 1.2.18 ASB - Calculating a Threshold
      • 1.2.19 Prescaler Range
      • 1.2.20 Acquisition Time
      • 1.2.21 ASB Channel Mapping
      • 1.2.22 Designing with the Analog System
      • 1.2.23 Analog System Clocks
      • 1.2.24 Analog System Builder and Flash Memory Block Basic Configuration
      • 1.2.25 Analog System Builder with Real Time Counter (RTC)
      • 1.2.26 Analog System Builder with ACM Access
    • 1.3 Analog System Builder Peripherals
    • 1.4 Flash Memory System Builder
    • 1.5 Revision History
    • 1 Microchip FPGA Support
    • 1 Microchip Information
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

1.2.8.5 Calibration Side Effects

Using calibration requires an extra 14 system clock latency for each conversion (that is, reduction in sampling rate) and an increase in tile count.

The actual tile count increase depends on your system clock frequency input in the ASB dialog. If it is greater than 60 MHz, then the tile count increase is ~470, otherwise it is ~370.

Related topics:

ASB Advanced Options

ASB Connectivity and Calibration

Analog System Builder Calibration Output Files

Rev: A

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