5.34.110 About Designer Tcl commands

A Tcl (Tool Command Language) file contains scripts for simple or complex tasks. You can run scripts from either the Windows or UNIX command line or store and run a series of Tcl commands in a “.tcl” batch file. You can also run scripts from within Designer.

Designer supports the following Tcl scripting commands. Tcl commands are case sensitive. However, their arguments are not.


Command	Action
add_probe	Adds a probe to an internal net in your design, using the original name from the optimized netlist in your design. Also, this command must be used in conjunction with the generate_probes command to generate a probed ADB file (see example below).
all_inputs	Returns an object representing all input and inout pins in the current design.
all_outputs	Returns an object representing all output and inout pins in the current design.
all_registers	Returns an object representing register pins or cells in the current scenario based on the given parameters.
are_all_source_files_current	Audits all source files and determines whether or not they are out of date/imported into the workspace.
backannotate	Extracts timing delays from your post layout data.
check_timing_constraints	Checks all timing constraints in the current timing scenario for validity.
clone_scenario	Creates a new timing scenario by duplicating an existing one.
close_design	Closes the current design.
compile	Performs design rule check and optimizes the input netlist before translating the source code into machine code.
create_clock	Creates a clock constraint on the specified ports/pins, or a virtual clock if no source is specified.
create_generated_clock	Creates an internally generated clock constraint on the ports/pins and defines its characteristics.
create_scenario	Creates a new timing scenario with the specified name.
delete_probe	Deletes a probe on nets in a probed ADB file.
delete_scenario	Deletes the specified timing scenario.
export	Converts a file from its current format into the specified file format, usually for use in another program.
extended_run_shell	Runs multiple iterations of layout through Designer.
generate_probes	Executes the probing and creates a new ADB file. This command is used in conjunction with the add_probe Tcl command (see example below).
get_cells	Returns an object representing the cells (instances) that match those specified in the pattern argument.
get_clocks	Returns an object representing the clock(s) that match those specified in the pattern argument in the current timing scenario.
get_current_scenario	Returns the name of the current timing scenario.
get_defvar	Returns the value of the Designer internal variable you specify.
get_design_filename	Returns the fully qualified path of the specified design file.
get_design_info	Returns detailed information about your design, depending on which arguments you specify.
get_nets	Returns an object representing the nets that match those specified in the pattern argument.
get_out_of_date_files	Audits all files returns a list of filenames that are out of date.
get_pins	Returns an object representing the pin(s) that match those specified in the pattern argument.
get_ports	Returns an object representing the port(s) that match those specified in the pattern argument.
import_aux	Imports the specified file as an auxiliary file, which are not audited and do not require you to re-compile the design.
import_source	Imports the specified file as a source file, which include your netlist and design constraints.
ioadvisor_apply_suggestion	Applies the suggestions for the selected attribute to the selected I/O(s).
ioadvisor_commit	Saves all changes in the I/O Advisor.
ioadvisor_restore	Restores the I/O Advisor to the initial state.
ioadvisor_restore_initial_value	Sets the current value for the selected attribute and I/Os to the initial value.
ioadvisor_set_outdrive	Sets the outdrive for the selected I/Os.
ioadvisor_set_outputload	Sets the output load for the selected I/Os.
ioadvisor_set_slew	Sets the slew for the selected I/Os.
is_design_loaded	Returns True if the design is loaded into Designer; otherwise, returns False.
is_design_modified	Returns True if the design has been modified since it was last compiled; otherwise, returns False.
is_design_state_complete	Returns True if the specified design state is complete (for example, you can inquire as to whether a die and package has been selected for the design); otherwise, returns False.
is_source_file_current	Audits the source file and determines whether or not the file is out of date / imported into the workspace.
layout	Place-and-route your design.
layout (advanced options for the SX family)	Sets advanced place-and-route features for SX family designs.
layout - Axcelerator	Sets advanced place-and-route features for Axcelerator family designs.
list_clocks	Returns details about all of the clock constraints in the current timing constraint scenario.
list_clock_latencies	Returns details about all of the clock latencies in the current timing constraint scenario.
list_clock_uncertainties	Returns the list of clock-to-clock uncertainty constraints for the current scenario.
list_disable_timings	Returns the list of disable timing constraints for the current scenario.
list_false_paths	Returns details about all of the false paths in the current timing constraint scenario.
list_generated_clocks	Returns details about all of the generated clock constraints in the current timing constraint scenario.
list_input_delays	Returns details about all of the input delay constraints in the current timing constraint scenario.
list_max_delays	Returns details about all of the maximum delay constraints in the current timing constraint scenario.
list_min_delays	Returns details about all of the minimum delay constraints in the current timing constraint scenario.
list_multicycle_paths	Returns details about all of the multicycle paths in the current timing constraint scenario.
list_objects	Returns a list of names of the objects in the specified list.
list_output_delays	Returns details about all of the output delay constraints in the current timing constraint scenario.
list_scenarios	Returns a list of names of all of the available timing scenarios.
new_design	Creates a new design (.adb) file in a specific location for a particular design family such as Axcelerator or ProASIC3.
open_design	Opens an existing design in the Designer software.
pin_assign	Assigns the named pin to the specified port but does not lock its assignment.
pin_commit	Saves the pin assignments to the design (.adb) file.
pin_fix	Locks the pin assignment for the specified port, so the pin cannot be moved during place-and-route.
pin_fix_all	Locks all the assigned pins on the device so they cannot be moved during place-and-route.
pin_unassign	Unassigns a specific pin from a specific port. The unassigned pin location is then available for other ports.
pin_unassign_all	Unassigns all pins from a specific port.
pin_unfix	Unlocks the specified pin from its port..
layout (advanced options for ProASIC	Sets advanced place-and-route features for ProASIC family designs.
remove_clock	Removes the specified clock constraint from the current timing scenario.
remove_clock_latency	Removes a clock source latency from the specified clock and from all edges of the clock.
remove_clock_uncertainty	Removes a clock-to-clock uncertainty from the current timing scenario by specifying either its exact arguments or its ID.
remove_disable_timing	Removes a disable timing constraint by specifying its arguments, or its ID.
remove_false_path	Removes a false path from the current timing scenario by specifying either its exact arguments or its ID.
remove_generated_clock	Removes the specified generated clock constraint from the current scenario.
remove_input_delay	Removes an input delay a clock on a port by specifying both the clocks and port names or the ID of the input_delay constraint to remove.
remove_max_delay	Removes a maximum delay constraint in the current timing scenario by specifying either its exact arguments or its ID.
remove_min_delay	Removes a minimum delay constraint in the current timing scenario by specifying either its exact arguments or its ID.
remove_multicycle_path	Removes a multicycle path constraint in the current timing scenario by specifying either its exact arguments or its ID.
remove_output_delay	Removes an ouput delay by specifying both the clocks and port names or the ID of the output_delay constraint to remove.
rename_scenario	Renames the specified timing scenario with the new name provided.
report	Generates the type of report you specify: Status, Timing, Timer Violations, Flip-flop, Power, Pin, or I/O Bank.
report (Activity and Hazards Power Report)	Reads a VCD file and reports transitions and hazards for each clock cycle of the VCD file.
report (Bottleneck) using SmartTime	Creates a bottleneck report.
report (Cycle Accurate Power Report)	Reports a power waveform with one power value per clock period or half-period instead of an average power for the whole simulation.
Report (Data History)	Reports new features and enhancements, bug fixes and known issues for the current release that may impact the power consumption of the design.
report (Datasheet) using SmartTime	Creates a datasheet report.
Report (Power)	Creates a Power report, which enables you to determine if you have any power consumption problems in your design.
Report (Power Scenario)	Creates a scenario power report, which enables you to enter a duration for a sequence of previously defined power modes and calculate the average power consumption and the excepted battery life for this sequence.
report (Timing) using SmartTime	Creates a timing report.
report (Timing violations) using SmartTime	Creates a timing violations report.
set_clock_latency	Defines the delay between an external clock source and the definition pin of a clock within SmartTime.
set_clock_uncertainty	Specifies a clock-to-clock uncertainty and returns the ID of the created constraint if the command succeeded.
set_current_scenario	Specifies the timing scenario for the Timing Analyzer to use.
save_design	Writes the design to the specified filename.
set_defvar	Sets the value of the Designer internal variable you specify >.
set_design	Specifies the design name, family and path in which Designer will process the design.
set_device	Specifies the type of device and its parameters.
set_disable_timing	Disables timing a.rcs within a cell and returns the ID of the created constraint.
set_false_path	Identifies paths that are considered false and excluded from the timing analysis in the current timing scenario.
set_input_delay	Creates an input delay on a port list by defining the arrival time of an input relative to a clock in the current scenario.
set_max_delay	Specifies the maximum delay for the timing paths in the current scenario.
set_min_delay	Specifies the minimum delay for the timing paths in the current scenario.
set_multicycle_path	Defines a path that takes multiple clock cycles in the current scenario.
set_output_delay	Defines the output delay of an output relative to a clock in the current scenario.
smartpower_add_new_custom_mode	Creates a new custom mode.
smartpower_add_new_scenario	Creates a new scenario.
smartpower_add_pin_in_domain	Adds a pin to either a Clock or Set domain.
smartpower_change_clock_statistics	Changes the default frequencies and probabilities for a specific domain.
smartpower_change_setofpin_statistics	Changes the default frequencies and probabilities for a specific set.
smartpower_commit	Saves the changes made in SmartPower to the design file (.adb) in Designer.
smartpower_create_domain	Creates a new clock or set domain.
smartpower_edit_custom_mode	Edits a custom mode.
smartpower_edit_scenario	Edits a scenario.
smartpower_initialize_clock_with_constraints	Initializes the clock frequency and the data frequency of a single clock domain with a specified clock name and the initialization options.
smartpower_init_do	Initializes the frequencies and probabilities for clocks, registers, set/reset nets, primary inputs, combinational outputs, enables and other sets of pins, and selects a mode for initialization.
smartpower_init_set_clocks_options	Initializes the clock frequency of all clock domains.
smartpower_init_set_combinational_options	Initializes the frequency and probability of all combinational outputs.
smartpower_init_set_enables_options	Initializes the clock frequency of all enable clocks with the initialization options.
smartpower_init_set_othersets_options	Initializes the frequency and probability of all other sets.
smartpower_init_set_primaryinputs_options	Initializes the frequency and probability of all primary inputs.
smartpower_init_set_registers_options	Initializes the frequency and probability of all register outputs.
smartpower_init_set_set_reset_options	Initializes the frequency and probability of all set/reset nets.
smartpower_init_setofpins_values	Initializes the frequency and probability of all sets of pins.
smartpower_remove_all_annotations	Removes all initialization annotations for the specified mode.
smartpower_remove_custom_mode	Removes a custom mode.
smartpower_remove_domain	Removes an existing domain.
smartpower_remove_file	Removes a VCD file from the specified mode.
smartpower_remove_pin_enable_rate	This command is obsolete and it is replaced by smartpower_remove_pin_probability
smartpower_remove_pin_frequency	Removes the frequency of an existing pin.
smartpower_remove_pin_of_domain	Removes a clock pin or a data pin from a Clock or Set domain, respectively.
smartpower_remove_pin_probability	Enables you to annotate the probability of a pin driving an enable pin.
smartpower_remove_scenario	Removes a scenario from the current design.
smartpower_remove_vcd	Removes an existing VCD file from a mode or entire design.
smartpower_restore	Restores previously committed constraints.
smartpower_set_battery_capacity	Sets the battery capacity.
smartpower_set_cooling	Sets the cooling style to one of the predefined types, or a custom value.
smartpower_set_mode_for_analysis	Sets the mode for cycle-accurate power analysis.
smartpower_set_operating_condition	Sets the operating conditions used in SmartPower to best, typical, or worst case.
smartpower_set_pin_enable_rate	This command is obsolete and is replaced by smartpower_set_pin_probability.
smartpower_set_pin_frequency	Sets the frequency of an existing pin.
smartpower_set_pin_probability	Enables you to annotate the probability of a pin driving an enable pin.
smartpower_set_preferences	Sets SmartPower preferences such as power unit, frequency unit, operating mode, operating conditions, and toggle.
smartpower_set_scenario_for_analysis	Sets the scenario for cycle-accurate power analysis.
smartpower_set_temperature_opcond	Sets the temperature in the operating conditions used in SmartPower.
smartpower_set_thermalmode	Sets the mode of computing junction temperature.
smartpower_set_voltage_opcond	Sets the voltage in the operating conditions used in SmartPower.
smartpower_temperature_opcond_set_design_wide	Sets the temperature for SmartPower design-wide operating conditions.
smartpower_temperature_opcond_set_mode_specific	Sets the temperature for SmartPower mode-specific operating conditions.
smartpower_voltage_opcond_set_design_wide	Sets the voltage settings for SmartPower design-wide operating conditions.
smartpower_voltage_opcond_set_mode_specific	Sets the voltage settings for SmartPower mode-specific use operating conditions.
st_create_set	Creates a set of paths to be analyzed.
st_commit	Saves the changes made in SmartTime to the design (.adb) file.
st_edit_set	Modifies the paths in a user set.
st_expand_path	Displays expanded path information (path details) for paths.
st_list_paths	Displays the list of paths in the same tabular format shown in SmartTime.
st_remove_set	Deletes a user set from the design.
st_restore	Restores constraints previously committed in SmartTime.
st_set_options	Sets options for timing analysis.
timer_add_clock_exception	Adds an exception to or from a pin with respect to a specified clock.
timer_add_pass	Adds the pin to the list of pins for which the path must be shown passing through in the timer.
timer_add_stop	Adds the specified pin to the list of pins through which the paths will not be displayed in the timer.
timer_commit	Saves the changes made to constraints in Timer into the Designer database.
timer_get_path	Displays the Timer path information in the Log window.
timer_get_clock_actuals	Displays the actual clock frequency in the Log window.
timer_get_clock_constraints	Displays the clock constraints (period/frequency and dutycycle) in the Log window.
timer_get_maxdelay	Displays the maximum delay constraint between two pins of a path in the Log window.timer_get_path_constraintsDisplays the path constraints set for maxdelay in the Timer in the Log window.
timer_remove_clock_exception	Removes the previously set clock constraint.
timer_remove_pass	Removes the previously entered path pass constraint.
timer_remove_stop	Removes the path stop constraint on the specified pin.timer_restoreRestores previously committed constraints.timer_setenv_clock_freqSets a required clock frequency, in MHz, for the specified clock.
timer_setenv_clock_period	Sets the clock period constraint for the specified clock.
timer_set_maxdelay	Adds a maximum delay constraint for the path.
timer_remove_all_constraints	Removes all the timing constraints previously entered in the Designer system.