5.34.102 Arguments

-hdl "VHDL | VERILOG"

Sets your project HDL type.

-auto_update_modelsim_ini "TRUE | FALSE"

Sets your auto-update modelsim.ini file option. TRUE updates the file automatically.

-auto_update_viewdraw_ini "TRUE | FALSE"

Sets your auto-update viewdraw.ini file option. TRUE updates the file automatically.

-block_mode "TRUE | FALSE"

Puts the Project Manager in Block mode, enables you to create blocks in your project.

-auto_generate_synth_hdl "TRUE | FALSE"

Auto-generates your HDL file after synthesis (when set to TRUE).

-auto_run_drc "TRUE | FALSE"

Auto-runs the design rule check immediately after synthesis (when set to TRUE).

-auto_generate_viewdraw_hdl "TRUE | FALSE"

Auto-generates your HDL netlist after a Save & Check in ViewDraw (when set to TRUE).

-auto_file_detection "TRUE | FALSE"

Automatically detects when new files have been added to the Libero IDE project folder (when set to TRUE).