5.34.101 Example

The example organizes a new stimulus file 'stim.vhd' using default settings.

-organize_sources -file stim.vhd -mode new -module stimulus -tool synthesis -use_default TRUE

project_settings

Modifies project flow settings for your Libero IDE project.

project_settings [-hdl "VHDL | VERILOG"] [-auto_update_modelsim_ini "TRUE | FALSE"] [-auto_update_viewdraw_ini "TRUE | FALSE"] [-block_mode "TRUE | FALSE"] [-auto_generate_synth_hdl "TRUE | FALSE"] [-auto_run_drc "TRUE | FALSE"] [-auto_generate_viewdraw_hdl "TRUE | FALSE"] [-auto_file_detection "TRUE | FALSE"]