3.9.17.4 SSMFBR – SSM Filter Bandwidth Register
| Name: | SSMFBR |
| Offset: | 0x0E4 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SSMPLDT | SSMHADT | SSMDFDT | SSMFID[2:0] | ||||||
| Access | R | R | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
0’. Bit 6 – Reserved Bit
0’. Bit 5 – SSMPLDT Sequencer State Machine PLL Lock Delay Time
0 = 13 μs
delay time in the PLL lock state machine1 = 63 μs delay time in
the PLL lock state machine The longer setting (SSMPLDT = 1) has
to be used if the filter bandwidth is less than 125
kHz.
Bit 4 – SSMHADT Sequencer State Machine Half Antenna Damping Delay Time
1’
to this bit halves the channel filter delay time in the antenna damping sequence of
the get telegram state machine.Bit 3 – SSMDFDT Sequencer State Machine Double Filter Delay Time
1’
to this bit doubles the channel filter delay time in the RX DSP enable state machine
and in the antenna damping sequence of the get telegram state machine. Bits 2:0 – SSMFID[2:0] Sequencer State Machine Filter Delay
|
SSMFID |
Delay Time in RX DSP Enable |
Delay Time in Antenna Damping |
Bandwidth of Channel Filter | |||
|---|---|---|---|---|---|---|
|
SSMDFDT = 0 |
SSMDFDT = 1 | SSMDFDT = SSMHADT |
SSMDFDT = 0 SSMHADT = 1 |
SSMDFDT = 1 SSMHADT = 0 | ||
| 0x0 | 380 µs | 760 µs | 380 µs | 190 µs | 760 µs | 25 kHz |
| 0x1 | 202.µs | 405 µs | 202.5 µs | 101.25 µs | 405 µs | 50 kHz |
| 0x2 | 135 µs | 270 µs | 135 µs | 62.5 µs | 270 µs | 80 kHz |
| 0x3 | 75 µs | 150 µs | 75 µs | 37.5 µs | 150 µs | 165 kHz |
| 0x4 | 58.5 µs | 117 µs | 58.5 µs | 29.25 µs | 117 µs | 235 kHz |
| 0x5 | 45 µs | 90 µs | 45 µs | 22.5 µs | 90 µs | 360 kHz |
| 0x6 | 380 µs | 760 µs | 380 µs | 190 µs | 760 µs | 25 kHz |
| 0x7 | 380 µs | 760 µs | 380 µs | 190 µs | 760 µs | 25 kHz |
