3.9.17.9 MSMSTR – Host State Machine
State Register
Name:
MSMSTR
Offset:
0x0E9
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
SSMMST[4:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 4:0 – SSMMST[4:0] Sequencer State
Machine Host State
This value gives the current
state of the host state machine. Reading this register triggers sampling of SSMSTR
and SSMXSR to get a consistent state of the entire SSM block. This value is intended
mainly for debugging. A read access to this register automatically updates the
SSMSTR and SSMXSR registers.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
