3.9.17.7 SSMIFR – SSM
Interrupt Flag Register
| Name: | SSMIFR |
| Offset: | 0x0E7 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | SSMIF | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – SSMIF Sequencer State
Machine Interrupt Flag
This flag is set to
‘1’ if the host state machine has reached the end of its
programmed sequence or has encountered an error and has completed operation. It is
cleared automatically if the SSM interrupt routine is executed or it can be reset
manually by writing a ‘1’ to this bit.
