3.9.17.5 SSMRR – SSM Run
Register
The host state machine
can be started and stopped by writing to the corresponding configuration bits. If
started, the state machine calls the sub-state machines as configured in the MSMCRx
registers and, if enabled in the SSMIMR register, requests an interrupt at the end of
operation. If necessary, all state machine operation can be stopped immediately by
setting the SSMST bit.| Name: | SSMRR |
| Offset: | 0x0E5 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | SSMST | SSMR | |
| Access | R | R | R | R | R | R | W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 1 – SSMST Sequencer State Machine Stop
Writing a ‘1’
to this bit immediately stops the host state machine and the currently running
sub-state machine and resets the SSMR bit. No interrupt is given by this
software-driven stop. SSMST is reset automatically after one clock cycle, and,
therefore, always reads ‘0’. After giving the stop signal to the
state machine, it is not defined in what state the design is in. Starting the shut
down state machine after the software-driven stop must be considered in order to put
the design back into a safe and known state.
Bit 0 – SSMR Sequencer State Machine Run
Writing a ‘1’
to this bit starts the host state machine. The bit is reset automatically when the
host state machine completes all configured sub-state machines or the software
writes a ‘1’ to the SSMST bit. Reading this bit is an indicator of
whether the state machine is running or completed its
operation.
