3.9.17.8 SSMIMR – SSM
Interrupt Mask Register
| Name: | SSMIMR |
| Offset: | 0x0E8 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | SSMIM | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – SSMIM Sequencer State
Machine Interrupt Mask
If this bit is set to
‘1’ and if global interrupts are enabled, the sequencer state
machine issues an interrupt when the SSMIF flag in SSMIFR is set. If SSMIM is
‘0’, no interrupt is requested when the host state machine
completes.
