Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
- 3.1 Overview
- 3.2 Static Memory Controller (SMC)
- 3.3 Universal DDR Memory Controller (UDDRC)
- 3.4 DDR/LPDDR Physical Interface (DDR3PHY)
  - 3.4.1 Description
  - 3.4.2 Embedded Characteristics
  - 3.4.3 Functional Description
  - 3.4.4 Register Summary
    - 3.4.4.1 DDR3PHY PHY Initialization Register
      DDR3PHY PHY Initialization Register
    - 3.4.4.2 DDR3PHY PHY General Configuration Register
      DDR3PHY PHY General Configuration Register
    - 3.4.4.3 DDR3PHY PHY General Status Register
      DDR3PHY PHY General Status Register
    - 3.4.4.4 DDR3PHY DLL General Control Register
      DDR3PHY DLL General Control Register
    - 3.4.4.5 DDR3PHY AC DLL Control Register
      DDR3PHY AC DLL Control Register
    - 3.4.4.6 DDR3PHY PHY Timing Register 0
      DDR3PHY PHY Timing Register 0
    - 3.4.4.7 DDR3PHY PHY Timing Register 1
      DDR3PHY PHY Timing Register 1
    - 3.4.4.8 DDR3PHY PHY Timing Register 2
      DDR3PHY PHY Timing Register 2
    - 3.4.4.9 DDR3PHY AC I/O Configuration Register
      DDR3PHY AC I/O Configuration Register
    - 3.4.4.10 DDR3PHY Data Byte Common Configuration Register
      DDR3PHY Data Byte Common Configuration Register
    - 3.4.4.11 DDR3PHY DDR System General Configuration Register
      DDR3PHY DDR System General Configuration Register
    - 3.4.4.12 DDR3PHY DRAM Configuration Register
      DDR3PHY DRAM Configuration Register
    - 3.4.4.13 DDR3PHY DRAM Timing Parameters Register 0
      DDR3PHY DRAM Timing Parameters Register 0
    - 3.4.4.14 DDR3PHY DRAM Timing Parameter Register 1
      DDR3PHY DRAM Timing Parameter Register 1
    - 3.4.4.15 DDR3PHY DRAM Timing Parameter Register 2
      DDR3PHY DRAM Timing Parameter Register 2
    - 3.4.4.16 DDR3PHY Mode Register 0 (MR0) (DDR3 Mode)
      DDR3PHY Mode Register 0 (MR0) (DDR3 Mode)
    - 3.4.4.17 DDR3PHY Mode Register 0 (MR0) (DDR2 Mode)
      DDR3PHY Mode Register 0 (MR0) (DDR2 Mode)
    - 3.4.4.18 DDR3PHY Mode Register 1 (MR1) (DDR3 Mode)
      DDR3PHY Mode Register 1 (MR1) (DDR3 Mode)
    - 3.4.4.19 DDR3PHY Mode Register 1 (MR1) (DDR2 Mode)
      DDR3PHY Mode Register 1 (MR1) (DDR2 Mode)
    - 3.4.4.20 DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode)
      DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode)
    - 3.4.4.21 DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode)
      DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode)
    - 3.4.4.22 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode)
    - 3.4.4.23 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode)
    - 3.4.4.24 DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode)
    - 3.4.4.25 DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR3 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR3 Mode)
    - 3.4.4.26 DDR3PHY Mode Register 3 (MR3) (DDR3 Mode)
      DDR3PHY Mode Register 3 (MR3) (DDR3 Mode)
    - 3.4.4.27 DDR3PHY Mode Register 3 (MR3) (DDR2 Mode)
      DDR3PHY Mode Register 3 (MR3) (DDR2 Mode)
    - 3.4.4.28 DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode)
      DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode)
    - 3.4.4.29 DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode)
      DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode)
    - 3.4.4.30 DDR3PHY ODT Configuration Register
      DDR3PHY ODT Configuration Register
    - 3.4.4.31 DDR3PHY Data Training Address Register
      DDR3PHY Data Training Address Register
    - 3.4.4.32 DDR3PHY Data Training Data Register 0
      DDR3PHY Data Training Data Register 0
    - 3.4.4.33 DDR3PHY Data Training Data Register 1
      DDR3PHY Data Training Data Register 1
    - 3.4.4.34 DDR3PHY DCU Address Register
      DDR3PHY DCU Address Register
    - 3.4.4.35 DDR3PHY DCU Data Register
      DDR3PHY DCU Data Register
    - 3.4.4.36 DDR3PHY DCU Run Register
      DDR3PHY DCU Run Register
    - 3.4.4.37 DDR3PHY DCU Loop Register
      DDR3PHY DCU Loop Register
    - 3.4.4.38 DDR3PHY DCU General Configuration Register
      DDR3PHY DCU General Configuration Register
    - 3.4.4.39 DDR3PHY DCU Timing Parameter Register
      DDR3PHY DCU Timing Parameter Register
    - 3.4.4.40 DDR3PHY DCU Status Register 0
      DDR3PHY DCU Status Register 0
    - 3.4.4.41 DDR3PHY DCU Status Register 1
      DDR3PHY DCU Status Register 1
    - 3.4.4.42 DDR3PHY BIST Run Register
      DDR3PHY BIST Run Register
    - 3.4.4.43 DDR3PHY BIST Word Count Register
      DDR3PHY BIST Word Count Register
    - 3.4.4.44 DDR3PHY BIST Mask 0 Register
      DDR3PHY BIST Mask 0 Register
    - 3.4.4.45 DDR3PHY BIST Mask 1 Register
      DDR3PHY BIST Mask 1 Register
    - 3.4.4.46 DDR3PHY BIST LFSR Seed Register
      DDR3PHY BIST LFSR Seed Register
    - 3.4.4.47 DDR3PHY BIST Address 0 Register
      DDR3PHY BIST Address 0 Register
    - 3.4.4.48 DDR3PHY BIST Address 1 Register
      DDR3PHY BIST Address 1 Register
    - 3.4.4.49 DDR3PHY BIST Address 2 Register
      DDR3PHY BIST Address 2 Register
    - 3.4.4.50 DDR3PHY BIST User Data Pattern Register
      DDR3PHY BIST User Data Pattern Register
    - 3.4.4.51 DDR3PHY General Status Register
      DDR3PHY General Status Register
    - 3.4.4.52 DDR3PHY Word Error Register
      DDR3PHY Word Error Register
    - 3.4.4.53 DDR3PHY BIST Bit Error 0 Register
      DDR3PHY BIST Bit Error 0 Register
    - 3.4.4.54 DDR3PHY BIST Bit Error 1 Register
      DDR3PHY BIST Bit Error 1 Register
    - 3.4.4.55 DDR3PHY BIST Bit Error 2 Register
      DDR3PHY BIST Bit Error 2 Register
    - 3.4.4.56 DDR3PHY BIST Word Count Status Register
      DDR3PHY BIST Word Count Status Register
    - 3.4.4.57 DDR3PHY Fail Word 0 Register
      DDR3PHY Fail Word 0 Register
    - 3.4.4.58 DDR3PHY Fail Word 1 Register
      DDR3PHY Fail Word 1 Register
    - 3.4.4.59 DDR3PHY ZQ Impedance Control Register 0
      DDR3PHY ZQ Impedance Control Register 0
    - 3.4.4.60 DDR3PHY ZQ Impedance Control Register 1
      DDR3PHY ZQ Impedance Control Register 1
    - 3.4.4.61 DDR3PHY ZQ Status Register 0
      DDR3PHY ZQ Status Register 0
    - 3.4.4.62 DDR3PHY ZQ Status Register 1
      DDR3PHY ZQ Status Register 1
    - 3.4.4.63 DDR3PHY Data Byte General Configuration Register
      DDR3PHY Data Byte General Configuration Register
    - 3.4.4.64 DDR3PHY Data Byte General Status Register 0
      DDR3PHY Data Byte General Status Register 0
    - 3.4.4.65 DDR3PHY Data Byte General Status Register 1
      DDR3PHY Data Byte General Status Register 1
    - 3.4.4.66 DDR3PHY Data Byte DLL Control Register
      DDR3PHY Data Byte DLL Control Register
    - 3.4.4.67 DDR3PHY Data Byte DDR_D Timing Register
      DDR3PHY Data Byte DDR_D Timing Register
    - 3.4.4.68 DDR3PHY Data Byte DQS Timing Register
      DDR3PHY Data Byte DQS Timing Register
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information

3.4.4.36 DDR3PHY DCU Run Register

Name:	DDR3PHY_DCURR
Offset:	0xC8
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	XCEN	RCEN	SCOF	SONF	NFAIL[7:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	NFAIL[3:0]				EADDR[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SADDR[3:0]				DINST[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 23 – XCEN Expected Compare Enable

If set, indicates that read data coming back from the SDRAM is compared with the expected data.

Bit 22 – RCEN Read Capture Enable

If set, indicates that read data coming back from the SDRAM is captured into the read data cache.

Bit 21 – SCOF Stop Capture On Full

If set, specifies that the capture of read data stops when the capture cache is full.

Bit 20 – SONF Stop On Nth Fail

If set, specifies that the execution of commands and the capture of read data stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command.

Bits 19:12 – NFAIL[7:0] Number of Failures

Specifies the number of failures after which the execution of commands and the capture of read data stop if SONF is set. Execution of commands and the capture of read data stop after (NFAIL+1) failures if SONF is set.

Bits 11:8 – EADDR[3:0] End Address

Cache word address where the execution of commands ends.

Bits 7:4 – SADDR[3:0] Start Address

Cache word address where the execution of commands begins.

Bits 3:0 – DINST[3:0] DCU Instruction

Selects the DCU command to be executed.

Value	Description
0	NOP: No operation
1	Run: Triggers the execution of commands in the command cache
2	Stop: Stops the execution of commands in the command cache.
3	Stop Loop: Stops the execution of an infinite loop in the command cache.
4	Reset: Resets all DCU run time registers
5–7	Reserved

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