3.4.4.63 DDR3PHY Data Byte General Configuration Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
								R0RVSL[2]
Access								R/W
Reset								1


Bit	15	14	13	12	11	10	9	8
	R0RVSL[1:0]		RTTOAL	RTTOH[1:0]		DQRTT	DQSRTT	DSEN[1]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	1	1	1	0


Bit	7	6	5	4	3	2	1	0
	DSEN[0]	DQSRPD	DXPDR	DXPDD	DXIOM	DQODT	DQSODT	DXEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	0	0	0	0	1

Bits 16:14 – R0RVSL[2:0] Rank 0 ITMD Read Valid System Latency

Used to specify the read valid system latency relative to the ideal placement of the ITMD read valid signal when DDR3PHY_DXCCR.RVSEL is set to 0. Power-up default is 011 (i.e. ideal placement of the read valid signal). The RVSL field is initially set by the DDR3PHY during automatic read valid training but this value can be overwritten by a direct write to this register.

Value	Description
0	Read valid system latency = ideal placement - 3
1	Read valid system latency = ideal placement - 2
2	Read valid system latency = ideal placement - 1
3	Read valid system latency = ideal placement
4	Read valid system latency = ideal placement + 1
5	Read valid system latency = ideal placement + 2
6	Read valid system latency = ideal placement +3
7	Reserved

Bit 13 – RTTOAL RTT On Additive Latency

Indicates when the ODT control of DDR_D/DDR_DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles.

Value	Description
0	ODT control is set to DQSODT/DQODT almost two cycles before read data preamble.
1	ODT control is set to DQSODT/DQODT almost one cycle before read data preamble.

Bits 12:11 – RTTOH[1:0] RTT Output Hold

Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control remains set to DQSODT for DDR_DQS or DQODT for DDR_D/DDR_DQM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble.

Bit 10 – DQRTT DDR_D Dynamic RTT Control

If set, indicates that the ODT control of DDR_D/DDR_DQM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to ‘0’) during any other cycle. If this bit is not set, then the ODT control of DDR_D SSTL I/Os is always set to the value in DQODT. Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 since LPDDR2/LPDDR3 does not require ODT to be on.

Bit 9 – DQSRTT DDR_DQS Dynamic RTT Control

If set, indicates that the ODT control of DDR_DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to ‘0’) during any other cycle. If this bit is not set, then the ODT control of DDR_DQS SSTL I/Os is always set to the value in DQSODT field. Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 since LPDDR2/LPDDR3 does not require ODT to be on.

Bits 8:7 – DSEN[1:0] Write DDR_DQS Enable

Controls whether the write DDR_DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether DDR_DQS is inverted. DDR_DQSN is always the inversion of DDR_DQS. These values are valid only when DDR_DQS/DDR_DQSN output enable is on, otherwise DDR_DQS/DDR_DQSN is tristated.

Value	Description
0	DDR_DQS disabled (driven to constant 0)
1	DDR_DQS toggling with normal polarity (default setting)
2	DDR_DQS toggling with inverted polarity
3	DDR_DQS disabled (driven to constant 1)

Bit 6 – DQSRPD DQSR Power Down

If set, powers down the PDQSR cell. This bit is ORed with the common PDR configuration bit (see DDR3PHY_DXCCR).

Bit 5 – DXPDR Data Power Down Receiver

When set, powers down the input receiver on I/O for DDR_D, DDR_DQM, and DDR_DQS/DDR_DQSN pins of the byte. This bit is ORed with the common PDR configuration bit (see DDR3PHY_DXCCR).

Bit 4 – DXPDD Data Power Down Driver

When set, powers down the output driver on I/O for DDR_D, DDR_DQM, and DDR_DQS/DDR_DQSN pins of the byte. This bit is ORed with the common PDD configuration bit (see DDR3PHY_DXCCR).

Bit 3 – DXIOM Data I/O Mode

Must be written to '0'.

Bit 2 – DQODT Data On-Die Termination

When set, enables the on-die termination on the I/O for DDR_D and DDR_DQM pins of the byte. This bit is ORed with the common data byte ODT configuration bit (see DDR3PHY_DXCCR).

Bit 1 – DQSODT DDR_DQS On-Die Termination

When set, enables the on-die termination on the I/O for DDR_DQS/DDR_DQSN pins of the byte. This bit is ORed with the common data byte ODT configuration bit (see DDR3PHY_DXCCR).

Bit 0 – DXEN Data Byte Enable

If set, enables the I/Os used on the data byte. Setting this bit to ‘0’ disables the byte, i.e. the data byte I/Os are put in Power-Down mode and the DLL of the data byte is put in Bypass mode. After changing a Byte Lane from disabled to enabled, the DLL for that Byte Lane must be reset and re-locked. Software can use DDR3PHY_PIR.DLLSRST and DLLLOCK to accomplish this (reset and re-locks all DLLs in the DDR3PHY).

Name:	DDR3PHY_DXxGCR
Offset:	0x01C0 + x*0x40 [x=0..1]
Reset:	0x00010E81
Property:	Read/Write