Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
- 3.1 Overview
- 3.2 Static Memory Controller (SMC)
- 3.3 Universal DDR Memory Controller (UDDRC)
- 3.4 DDR/LPDDR Physical Interface (DDR3PHY)
  - 3.4.1 Description
  - 3.4.2 Embedded Characteristics
  - 3.4.3 Functional Description
  - 3.4.4 Register Summary
    - 3.4.4.1 DDR3PHY PHY Initialization Register
      DDR3PHY PHY Initialization Register
    - 3.4.4.2 DDR3PHY PHY General Configuration Register
      DDR3PHY PHY General Configuration Register
    - 3.4.4.3 DDR3PHY PHY General Status Register
      DDR3PHY PHY General Status Register
    - 3.4.4.4 DDR3PHY DLL General Control Register
      DDR3PHY DLL General Control Register
    - 3.4.4.5 DDR3PHY AC DLL Control Register
      DDR3PHY AC DLL Control Register
    - 3.4.4.6 DDR3PHY PHY Timing Register 0
      DDR3PHY PHY Timing Register 0
    - 3.4.4.7 DDR3PHY PHY Timing Register 1
      DDR3PHY PHY Timing Register 1
    - 3.4.4.8 DDR3PHY PHY Timing Register 2
      DDR3PHY PHY Timing Register 2
    - 3.4.4.9 DDR3PHY AC I/O Configuration Register
      DDR3PHY AC I/O Configuration Register
    - 3.4.4.10 DDR3PHY Data Byte Common Configuration Register
      DDR3PHY Data Byte Common Configuration Register
    - 3.4.4.11 DDR3PHY DDR System General Configuration Register
      DDR3PHY DDR System General Configuration Register
    - 3.4.4.12 DDR3PHY DRAM Configuration Register
      DDR3PHY DRAM Configuration Register
    - 3.4.4.13 DDR3PHY DRAM Timing Parameters Register 0
      DDR3PHY DRAM Timing Parameters Register 0
    - 3.4.4.14 DDR3PHY DRAM Timing Parameter Register 1
      DDR3PHY DRAM Timing Parameter Register 1
    - 3.4.4.15 DDR3PHY DRAM Timing Parameter Register 2
      DDR3PHY DRAM Timing Parameter Register 2
    - 3.4.4.16 DDR3PHY Mode Register 0 (MR0) (DDR3 Mode)
      DDR3PHY Mode Register 0 (MR0) (DDR3 Mode)
    - 3.4.4.17 DDR3PHY Mode Register 0 (MR0) (DDR2 Mode)
      DDR3PHY Mode Register 0 (MR0) (DDR2 Mode)
    - 3.4.4.18 DDR3PHY Mode Register 1 (MR1) (DDR3 Mode)
      DDR3PHY Mode Register 1 (MR1) (DDR3 Mode)
    - 3.4.4.19 DDR3PHY Mode Register 1 (MR1) (DDR2 Mode)
      DDR3PHY Mode Register 1 (MR1) (DDR2 Mode)
    - 3.4.4.20 DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode)
      DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode)
    - 3.4.4.21 DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode)
      DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode)
    - 3.4.4.22 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode)
    - 3.4.4.23 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode)
    - 3.4.4.24 DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode)
    - 3.4.4.25 DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR3 Mode)
      DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR3 Mode)
    - 3.4.4.26 DDR3PHY Mode Register 3 (MR3) (DDR3 Mode)
      DDR3PHY Mode Register 3 (MR3) (DDR3 Mode)
    - 3.4.4.27 DDR3PHY Mode Register 3 (MR3) (DDR2 Mode)
      DDR3PHY Mode Register 3 (MR3) (DDR2 Mode)
    - 3.4.4.28 DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode)
      DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode)
    - 3.4.4.29 DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode)
      DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode)
    - 3.4.4.30 DDR3PHY ODT Configuration Register
      DDR3PHY ODT Configuration Register
    - 3.4.4.31 DDR3PHY Data Training Address Register
      DDR3PHY Data Training Address Register
    - 3.4.4.32 DDR3PHY Data Training Data Register 0
      DDR3PHY Data Training Data Register 0
    - 3.4.4.33 DDR3PHY Data Training Data Register 1
      DDR3PHY Data Training Data Register 1
    - 3.4.4.34 DDR3PHY DCU Address Register
      DDR3PHY DCU Address Register
    - 3.4.4.35 DDR3PHY DCU Data Register
      DDR3PHY DCU Data Register
    - 3.4.4.36 DDR3PHY DCU Run Register
      DDR3PHY DCU Run Register
    - 3.4.4.37 DDR3PHY DCU Loop Register
      DDR3PHY DCU Loop Register
    - 3.4.4.38 DDR3PHY DCU General Configuration Register
      DDR3PHY DCU General Configuration Register
    - 3.4.4.39 DDR3PHY DCU Timing Parameter Register
      DDR3PHY DCU Timing Parameter Register
    - 3.4.4.40 DDR3PHY DCU Status Register 0
      DDR3PHY DCU Status Register 0
    - 3.4.4.41 DDR3PHY DCU Status Register 1
      DDR3PHY DCU Status Register 1
    - 3.4.4.42 DDR3PHY BIST Run Register
      DDR3PHY BIST Run Register
    - 3.4.4.43 DDR3PHY BIST Word Count Register
      DDR3PHY BIST Word Count Register
    - 3.4.4.44 DDR3PHY BIST Mask 0 Register
      DDR3PHY BIST Mask 0 Register
    - 3.4.4.45 DDR3PHY BIST Mask 1 Register
      DDR3PHY BIST Mask 1 Register
    - 3.4.4.46 DDR3PHY BIST LFSR Seed Register
      DDR3PHY BIST LFSR Seed Register
    - 3.4.4.47 DDR3PHY BIST Address 0 Register
      DDR3PHY BIST Address 0 Register
    - 3.4.4.48 DDR3PHY BIST Address 1 Register
      DDR3PHY BIST Address 1 Register
    - 3.4.4.49 DDR3PHY BIST Address 2 Register
      DDR3PHY BIST Address 2 Register
    - 3.4.4.50 DDR3PHY BIST User Data Pattern Register
      DDR3PHY BIST User Data Pattern Register
    - 3.4.4.51 DDR3PHY General Status Register
      DDR3PHY General Status Register
    - 3.4.4.52 DDR3PHY Word Error Register
      DDR3PHY Word Error Register
    - 3.4.4.53 DDR3PHY BIST Bit Error 0 Register
      DDR3PHY BIST Bit Error 0 Register
    - 3.4.4.54 DDR3PHY BIST Bit Error 1 Register
      DDR3PHY BIST Bit Error 1 Register
    - 3.4.4.55 DDR3PHY BIST Bit Error 2 Register
      DDR3PHY BIST Bit Error 2 Register
    - 3.4.4.56 DDR3PHY BIST Word Count Status Register
      DDR3PHY BIST Word Count Status Register
    - 3.4.4.57 DDR3PHY Fail Word 0 Register
      DDR3PHY Fail Word 0 Register
    - 3.4.4.58 DDR3PHY Fail Word 1 Register
      DDR3PHY Fail Word 1 Register
    - 3.4.4.59 DDR3PHY ZQ Impedance Control Register 0
      DDR3PHY ZQ Impedance Control Register 0
    - 3.4.4.60 DDR3PHY ZQ Impedance Control Register 1
      DDR3PHY ZQ Impedance Control Register 1
    - 3.4.4.61 DDR3PHY ZQ Status Register 0
      DDR3PHY ZQ Status Register 0
    - 3.4.4.62 DDR3PHY ZQ Status Register 1
      DDR3PHY ZQ Status Register 1
    - 3.4.4.63 DDR3PHY Data Byte General Configuration Register
      DDR3PHY Data Byte General Configuration Register
    - 3.4.4.64 DDR3PHY Data Byte General Status Register 0
      DDR3PHY Data Byte General Status Register 0
    - 3.4.4.65 DDR3PHY Data Byte General Status Register 1
      DDR3PHY Data Byte General Status Register 1
    - 3.4.4.66 DDR3PHY Data Byte DLL Control Register
      DDR3PHY Data Byte DLL Control Register
    - 3.4.4.67 DDR3PHY Data Byte DDR_D Timing Register
      DDR3PHY Data Byte DDR_D Timing Register
    - 3.4.4.68 DDR3PHY Data Byte DQS Timing Register
      DDR3PHY Data Byte DQS Timing Register
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information

3.4.4.6 DDR3PHY PHY Timing Register 0

Name:	DDR3PHY_PTR0
Offset:	0x18
Reset:	0x0022AF9B
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			TITMSRST[3:0]				TDLLLOCK[11:10]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	0	0	0	1	0


Bit	15	14	13	12	11	10	9	8
	TDLLLOCK[9:2]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	1	0	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	TDLLLOCK[1:0]		TDLLSRST[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	1	1	0	1	1

Bits 21:18 – TITMSRST[3:0] ITM Soft Reset Time

Number of configuration clock (PLLDDR/4) cycles during which the ITM soft reset pin must remain asserted when the soft reset is applied to the ITMs. This must correspond to a value that is equal to or more than 8 PLLDDR clock cycles.

Bits 17:6 – TDLLLOCK[11:0] DLL Lock Time

Number of configuration clock (PLLDDR/4) cycles for the DLL to stabilize and lock, i.e. number of clock cycles from when the DLL reset pin is de-asserted to when the DLL has locked and is ready for use. Default value corresponds to 5.12 µs at 533 MHz.

Bits 5:0 – TDLLSRST[5:0] DLL Soft Reset Time

Number of configuration clock (PLLDDR/4) cycles during which the DLL soft reset pin must remain asserted when the soft reset is triggered in DDR3PHY_PIR. This must correspond to a value that is equal to or more than 50 ns or 8 controller clock cycles, whichever is bigger. Default value corresponds to 50 ns at 533 MHz.

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