3.4.4.68 DDR3PHY Data Byte DQS Timing Register

Name: DDR3PHY_DXxDQSTR
Offset: 0x01D4 + x*0x40 [x=0..1]
Reset: 0x01B02000
Property: Read/Write

Bit 3130292827262524 
   DMDLY[3:0]DQSNDLY[2:1] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000001 
Bit 2322212019181716 
 DQSNDLY[0]DQSDLY[2:0]     
Access R/WR/WR/WR/W 
Reset 1011 
Bit 15141312111098 
   R0DGPS[1:0]     
Access R/WR/W 
Reset 10 
Bit 76543210 
      R0DGSL[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 29:26 – DMDLY[3:0] DDR_DQM Delay

Used to adjust the delay of the data mask relative to the nominal delay that is matched to the delay of the data strobes through the client DLL and clock tree. The lower two bits of the DMDLY controls the delay for the data clocked by DDR_DQS, while the higher two bits control the delay for the data clocked by DDR_DQSN.
ValueDescription
0 Nominal delay
1 Nominal delay + 1 step
2 Nominal delay + 2 steps
3 Nominal delay + 3 steps

Bits 25:23 – DQSNDLY[2:0] DDR_DQSN Delay

Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the client DLL and clock tree. DQSDLY controls the delay on DQS strobe and DQSNDLY controls the delay on DDR_DQSN.
Note: After changing this value, an ITM soft reset (DDR3PHY_PIR.ITMSRST=1, plus DDR3PHY_PIR.INIT=1) must be issued.
ValueDescription
0 Nominal delay - 3 steps
1 Nominal delay - 2 steps
2 Nominal delay - 1 step
3 Nominal delay
4 Nominal delay + 1 step
5 Nominal delay + 2 steps
6 Nominal delay + 3 steps
7 Nominal delay + 4 steps

Bits 22:20 – DQSDLY[2:0] DQS Delay

Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the client DLL and clock tree. DQSDLY controls the delay on DDR_DQS strobe and DQSNDLY controls the delay on DDR_DQSN.
Note: After changing this value, an ITM soft reset (DDR3PHY_PIR.ITMSRST=1, plus DDR3PHY_PIR.INIT=1) must be issued.
ValueDescription
0 Nominal delay - 3 steps
1 Nominal delay - 2 steps
2 Nominal delay - 1 step
3 Nominal delay
4 Nominal delay + 1 step
5 Nominal delay + 2 steps
6 Nominal delay + 3 steps
7 Nominal delay + 4 steps

Bits 13:12 – R0DGPS[1:0] Rank 0 DQS Gating Phase Select

Selects the clock used to enable the data strobes during read so that the value of the data strobes before and after the preamble/postamble are filtered out. The R0DGPS field is initially set by the DDR3PHY during automatic DDR_DQS data training and subsequently updated during data strobe drift compensation. However, this value can be overwritten by a direct write to this register, and the automatic update during DDR_DQS drift compensation can be disabled using DDR3PHY_PGCR.
ValueDescription
0 90° clock (clk90)
1 180° clock (clk180)
2 270° clock (clk270)
3 360° clock (clk0)

Bits 2:0 – R0DGSL[2:0] Rank 0 DQS Gating System Latency

Used to increase the number of clock cycles needed to expect valid DDR read data by up to five extra clock cycles. This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL field is initially set by the DDR3PHY during automatic DDR_DQS data training but this value can be overwritten by a direct write to this register.
ValueDescription
0 No extra clock cycles
1 1 extra clock cycle
2 2 extra clock cycles
3 3 extra clock cycles
4 4 extra clock cycles
5 5 extra clock cycles
6 Reserved
7 Reserved