3.6.2.4.7 SOC_AXI_TARGET
(Ask a Question)This is an SoC integration parameter to allow integrating HLS-generated modules into a custom user-defined SmartDesign system. The parameter specifies the AXI target interface in the user-defined SmartDesign system where the HLS module's AXI initiator interface can connect to. This AXI target interface is used by the HLS modules to access shared memory (DDR) directly.
Please refer to Soc Integration Parameters in 3.5.1.27 User-defined SmartDesign for more details on using this Tcl parameter.
- Category
- HLS Constraints
- Value Type
- String
- Default Value (Based on Icicle SoC reference design)
- AXI2AXI_FROM_HLS:AXI4_SLAVE
- Dependencies
- None
- Applicable Flows
- SoC Flow Only
- Test Status
- Actively in-use
- Examples
set_parameter SOC_AXI_TARGET AXI2AXI_FROM_HLS:AXI4_SLAVE