3.6.2.4.13 SOC_FABRIC_BASE_ADDRESS
(Ask a Question)This is an SoC integration parameter to allow integrating HLS-generated modules into a custom user-defined SmartDesign system. The parameter specifies the base address of the CPU memory space that is reserved for all HLS modules. The control registers and on-chip memory buffers of HLS modules are allocated and mapped within this memory window. This address is also used to configure the AXI interconnect that HLS modules connect to.
Note that the value for the parameter is specified in hexadecimal format and must be prefixed with 0x.
Please refer to Soc Integration Parameters in 3.5.1.27 User-defined SmartDesign for more details on how to use this Tcl parameter.
- Category
- HLS Constraints
- Value Type
- Hexadecimal
- Default Value (Based on Icicle SoC reference design)
- 0x70000000
- Dependencies
- None
- Applicable Flows
- SoC Flow Only
- Test Status
- Actively in-use
- Examples
set_parameter SOC_FABRIC_BASE_ADDRESS 0x70000000