3.6.2.4.10 SOC_CPU_MEM_BASE_ADDRESS
(Ask a Question)This is an SoC integration parameter to allow integrating HLS-generated modules into a custom user-defined SmartDesign system. The parameter specifies the base address of the memory window in the shared memory space (DDR) that can be accessed by the HLS module's AXI initiator interfaces. This address is used to configure the AXI interconnect that HLS modules connect to for accessing the shared memory.
Note that the value for the parameter is specified in hexadecimal format and must be prefixed with 0x.
Please refer to Soc Integration Parameters in 3.5.1.27 User-defined SmartDesign for more details on how to use this Tcl parameter.
- Category
- HLS Constraints
- Value Type
- Hexadecimal
- Default Value (Based on Icicle SoC reference design)
- 0x80000000
- Dependencies
- None
- Applicable Flows
- SoC Flow Only
- Test Status
- Actively in-use
- Examples
set_parameter SOC_CPU_MEM_BASE_ADDRESS 0x80000000