3.6.2.4.21 USE_FIFO_FOR_PIPELINE_REG
(Ask a Question)In a pipeline circuit where multiple stages of the circuit are concurrently active and processing different loop iterations (or function calls), pipeline registers are used to retain and propagate a variable value from the value-producing stage to the value-use stage. The pipeline registers are essentially a chain of shift registers with additional control logic. When the chain of pipeline registers is long, it may be more resource-efficient to implement the pipeline registers as a block-RAM FIFO rather than shift registers.
When this parameter is enabled, SmartHLS™ will examine each chain of pipeline registers and use the implementation (FIFO or shift register) that is estimated to be more resource-efficient.
- Category
- HLS Constraint
- Value Type
- Integer
- Valid Values
- 0, 1
- Default Value
- 1
- Location Where Default is Specified
examples/legup.tcl- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter USE_FIFO_FOR_PIPELINE_REG 1