3.6.2.4.5 MULTIPLY_SPLITTING_FULLY_PIPELINED
(Ask a Question)Multipliers are implemented in Math (DSP) blocks. When this constraint is set to 0, only the input register of each Math block is used, whereas when it is set to 1, both the input and output registers of each Math block are used. Utilizing just the input register will result in lower latency but utilizing both input and output registers will result in higher Fmax.
When 3.6.2.4.4 ENABLE_AUTOMATIC_MULTIPLY_MODE_SETTING is set to 1, which is the default, SmartHLS™ will automatically decide which multiplier mode should be used based on the target clock period constraint.
- Category
- HLS Constraints
- Value Type
- Boolean
- Valid Values
- 0, 1
- Default Value
- 0
- Location Where Default is Specified
examples/legup.tcl- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter MULTIPLY_SPLITTING_FULLY_PIPELINED 1