3.6.2.4.3 ENABLE_AUTOMATIC_MEMORY_LATENCY_SETTING

Enable determining memory latency for reads automatically according to the target clock period and timing model of the board. Memory latency is set to 2 when the target clock period is less than the delay of memory for the target device, otherwise is set to 1. Increasing the memory latency can result in higher circuit Fmax at the expense of higher circuit latency. The auto-determined latency can be found in the 3.5.1.23.1.4 Memory Usage section of SmartHLS™ report.

Setting the operation latency for a RAM will override the latency automatically calculated. See 3.6.2.2.6 set_operation_latency for a list of valid memory port latency. The threshold for switching are listed in the table below.

DeviceUse Memory Latency of 2 when Target Period is less than (ns)
PolarFire, PolarFireSoC4.167
IGLOO2, SmartFusion24.167

ENABLE_AUTOMATIC_MEMORY_LATENCY_SETTING controls the latency for the following memory constraints. Each constraint can be used with set_operation_latency <Name> <latency> to override the auto-determined latency.

NameDescription
local_memory_portControls the memory latency of 3.5.3.2.1 Local Memory used by a single function.
shared_local_memory_portControls the memory latency of 3.5.3.2.2 Shared-Local Memory shared by multiple functions.
axi_slave_ram_memory_portControls the memory latency of 3.5.1.18.3.4 Legacy AXI4 Slave Interface
memory_portControls the memory latency of 3.5.3.2.3.1 Memory Controller

SmartHLS does not automatically determine the latency for external_memory_port as it is only for creating an interface with the RAMs outside of the circuit. However, for 3.5.1.3 SmartHLS SoC Flow, external_memory_port controls the latency for the on-chip memory buffers.

Category
HLS Constraints
Value Type
Boolean
Valid Values
0, 1
Default Value
1
Location Where Default is Specified
examples/legup.tcl
Dependencies
None
Applicable Flows
All devices and flows
Test Status
Actively in-use
Examples
set_parameter ENABLE_AUTOMATIC_MEMORY_LATENCY_SETTING 1