49.4 Power Supply DC Module Electrical Specifications

Table 49-5. Power Supply DC Module Electrical Specifications
DC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
REG_2	VDD33_CIN⁽¹⁾	VDD33 Input Bypass parallel Capacitor pair	—	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_2	VDD33_CIN⁽¹⁾	VDD33 Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_3	PMU_VDDIO_CIN⁽¹⁾	PMU_VDDIO Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_3	PMU_VDDIO_CIN⁽¹⁾	PMU_VDDIO Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_4	PMU_VDDP_CIN⁽¹⁾	PMU_VDDP Input Bypass parallel Capacitor pair	—	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_4	PMU_VDDP_CIN⁽¹⁾	PMU_VDDP Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_5	FAVDD_CIN⁽¹⁾	FAVDD Input Bypass parallel Capacitor pair	—	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_5	FAVDD_CIN⁽¹⁾	FAVDD Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic X7R/X5R with ESR <0.5Ω depending on temperature
REG_6	AVDD_CIN⁽¹⁾	AVDD Input Bypass parallel Capacitor pair	—	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_6	AVDD_CIN⁽¹⁾	AVDD Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_7	VUSB_C_IN⁽¹⁾	USB Power pin bypass capacitance	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_7	VUSB_C_IN⁽¹⁾	USB Power pin bypass capacitance	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_8	BUCK_PA_CIN⁽¹⁾	BUCK_PA Input Bypass Capacitor	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_8	BUCK_PA_CIN⁽¹⁾	BUCK_PA Input Bypass Capacitor	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_9	CLDO_BUCK_CIN⁽¹⁾	CLDO_BUCK Input Bypass Capacitor	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_9	CLDO_BUCK_CIN⁽¹⁾	CLDO_BUCK Input Bypass Capacitor	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_10	CLDO_IN_CIN⁽¹⁾	CLDO_IN Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_10	CLDO_IN_CIN⁽¹⁾	CLDO_IN Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_11	CLDO_OUT_CIN⁽¹⁾	CLDO_OUT Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_11	CLDO_OUT_CIN⁽¹⁾	CLDO_OUT Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_12	VDD_RF_CIN⁽¹⁾	VDD_RF Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_12	VDD_RF_CIN⁽¹⁾	VDD_RF Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_13	RF_LDO_OUT_CIN⁽¹⁾	RF_LDO_OUT Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_13	RF_LDO_OUT_CIN⁽¹⁾	RF_LDO_OUT Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_14	SOC_LDO_IN_CIN⁽¹⁾	SOC_LDO, PLL_VDD Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_14	SOC_LDO_IN_CIN⁽¹⁾	SOC_LDO, PLL_VDD Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_15	AVDD_LEXT⁽³⁾	AVDD series Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600Ω at 100 MHz
REG_16	AVDD_LEXT⁽³⁾	Ferrite Bead current Rating	700	—	—	mA
REG_17	VBUCK_LEXT ^{(4, 5)}	Buck Regulator Inductor Inductance	—	4.7	—	µH	Shielded Inductor ONLY
REG_18	VBUCK_LEXT ^{(4, 5)}	Inductor DCR (DC Resistance)	—	—	0.288	Ω	—
REG_21	VBUCK_CEXT	Buck Regulator Bulk Capacitor Capacitance	—	10	—	µF	—
REG_22	VBUCK_CEXT	Capacitor ESR	—	—	0.01	Ω	—
REG_23	CLDO_LEXT	BUCK_PA/CLDO_BUCK Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600Ω at 100 MHz
REG_24	CLDO_LEXT	Ferrite Bead current Rating	700	—	—	mA
REG_25	CLDO_OUT_LEXT	CLDO_OUT Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600Ω at 100 MHz
REG_26	CLDO_OUT_LEXT	Ferrite Bead current Rating	700	—	—	mA
REG_27	SOC_LDO_LEXT	SOC_LDO_IN/PLL_VDD_IN Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600Ω at 100 MHz
REG_28	SOC_LDO_LEXT	Ferrite Bead current Rating	700	—	—	mA
REG_37	VDD33/VDDIO ⁽²⁾	VDD/VDDIO Input Voltage Range	1.9	3.3	3.6	V	—
REG_39	AVDD ⁽²⁾	AVDD Input Voltage Range	>= 1.9 VDD33-0.3	—	VDD33+0.3 <= 3.6	V	—
REG_41	VUSB3V3	VUSB3V3 Input Voltage Range	3	—	3.6	V	—
PMU Specification (MLDO Mode)
REG_43	MLDO_V_OUT	Output Voltage Range	—	1.35	—	V	—
REG_45	MLDO_V_IN	Input Voltage Range (Same as VDD/VDDIO)	1.9	3.3	3.6	V	—
PMU Specification (Buck Mode)
REG_67	BUCK_V_OUT	Output Voltage Range	—	1.35	—	V	—
REG_69	BUCK_V_IN	Input Voltage Range (Same as VDD/VDDIO)	2.4	3.3	3.6	V	—
CLDO Specification
REG_93	CLDO_V_IN	Input Voltage Range (Output from PMU)	1.3	1.35	1.4	V	—
REG_94	CLDO_V_OUT	Output Voltage Range	—	1.2	—	V	—
POR, BOR, RESET Specification
REG_105	SVDD_R	VDD Rise Ramp Rate to Ensure Internal Power-on Reset Signal	—	0.0055	0.011	V/µs	600 µs (typical) – 30 µs (minimum) at 3.3V
REG_107	SVDD_F	VDD Falling Ramp Rate to Ensure Internal Power-on Reset Signal	—	0.0055	0.011	V/µs	600 µs (typical) – 30 µs (minimum) at 3.3V
REG_109	VPOR+	Power-on Reset (voltage threshold level on VDD rising)	1.53	1.55	1.61	V	VDD33/VDDIO voltage must remain at VSS for a minimum of 200 µs to ensure POR. VDDIO Power-up/Power-down (see parameter REG_105, VDDIO Ramp Rate)
REG_111	VPOR-	Power-on Reset (voltage threshold level on VDD falling)	1.52	1.55	1.59	V	VDD33/VDDIO voltage must remain at VSS for a minimum of 200 µs to ensure POR. VDDIO Power-up/Power-down (see parameter REG_107, VDDIO Ramp Rate)
REG_113	VBOR33	BOR33 Voltage on VDD transition high to low	—	1.802	—	V	—
REG_115	VBOR33_LH	BOR33 Voltage on VDD transition low to high	—	1.834	—	V	—
REG_119	VBOR33_HYS	Brown-out Hysteresis	25	32	46	mV	—
REG_121	VBOR12	BOR12 (1.2V) Voltage transition high to low	—	1.1	—	V	—
REG_123	VBOR12_LH	BOR12 Voltage transition low to high	—	1.1	—	V	—
REG_125	VBOR12_HYS	Brown-out Hysteresis	2	4	10	mV	—
REG_127	VZPBOR33	Zero Power BOR (high to low)	—	1.787	—	V	—
REG_128	VZPBOR33_LH	Zero Power BOR (low to high)	—	1.85	—	V	—
REG_129	T_PU	Power-up Period (internal regulator enabled)	—	0.650	1.2	ms	Time till PMU, CLDO output are available
REG_135	T_SYSDLY	System Delay Period (without security)	—	4	—	ms	Before CPU start executing instruction from Flash. Includes Reload Device Configuration Fuses, Boot ROM execution time with authentication disable
REG_139	T_RST	External RESET valid active pulse width (low)	3	—	—	µs	Minimum reset active time to guarantee MCU reset for the SoC. No filter circuit
REG_139	T_RST	External RESET valid active pulse width (low)	13	—	—	µs	Minimum reset active time to guarantee MCU reset for the PIC32WM-BZ6 module. Reset filter circuit inside the module
Note: All bypass caps must be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU. Each primary power supply group VDDIO, AVDD must have one bulk capacitor and all power pins everywhere a 100 nF bypass cap. VDD33/VDDIO and AVDD must be at the same voltage level. Ferrite Bead ISAT(min) ≥ (IDD(maximum) × 1.15). User must select either MLDO or BUCK Mode. The modes are exclusive of each other. Buck Inductor ISAT(min) ≥ ((ICAPACITOR + IVDDCORE_MAX) × 1.2) when BUCK mode enabled (Shielded inductor only). Given: BUCK VSW output pin impedance = ~4Ω Buck Inductor DCR = ~0.2Ω (check Inductor Manufacturing Specification) C = VDDCORE Bypass Capacitance RVSW = VSW output pin impedance + Buck Inductor DCR e = 2.71828 Recommended Inductor ISAT margin 25% VDDCORE bypass bulk capacitor charging current through inductor: ICAPACITOR = (VDDCORE/RVSW)×e^^(-t/RC) where, t = 0 is worst case. Therefore: Inductor ISAT (maximum): = ((ICAPACITOR + IVDDCORE_PEAK_SURGE) × 1.25) = (((VDDCORE/RVSW)×e^^(-t/RC) + IVDDCORE_PEAK_SURGE) × 1.25) Example calculation: VDDCORE bypass capacitors = 4.7 µf + 100 nF IVDDCORE_PEAK_SURGE = 120 mA Inductor ISAT (maximum): = (((VDDCORE / RVSW)×e^^(-t/RC) + IVDDCORE_PEAK_SURGE) × 1.25) = (((1.2/4.2) × 2.71828-(0/4.3×4.8 µF) + 120 mA) × 1.25) = (((286 mA × 1) + 120 mA) × 1.25) = ((286 mA + 120 mA) × 1.25) = ~508 mA