49.24 QSPI Module Electrical Specifications

Table 49-32. QSPI Module Electrical Specifications
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions⁽²⁾
QSPI_1	FCLK	QSPI Serial Clock Frequency (DIRECT)	—	—	32	MHz	Host SDR Transfer mode 0 and 3 VDDIOx = 3.3V, C_LOAD= 20 pF_(MAXIMUM)
			—	—	32	MHz	Host SDR Transfer mode 0 and 3 VDDIOx = 1.9V, C_LOAD = 20 pF_(MAXIMUM)
			—	—	16	MHz	Host DDR Transfer mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0) VDDIOx = 3.3V, C_LOAD = 20 pF_(MAXIMUM)
			—	—	16	MHz	Host DDR Transfer mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0) VDDIOx = 1.9V, C_LOAD = 20 pF_(MAXIMUM)
	FCLK	QSPI Serial Clock Frequency(Remappable PPS)	—	—	16	MHz	Host SDR Transfer mode 0 and 3 VDDIOx = 3.3V, C_LOAD = 20 pF_(MAXIMUM)
			—	—	16	MHz	Host SDR Transfer mode 0 and 3 VDDIOx = 1.9V, C_LOAD = 20 pF_(MAXIMUM)
			—	—	8	MHz	Host DDR Transfer mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0) VDDIOx = 3.3V, C_LOAD = 20 pF_(MAXIMUM)
			—	—	8	MHz	Host DDR Transfer mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0) VDDIOx = 1.9V, C_LOAD = 20 pF_(MAXIMUM)
QSPI_3	TSCKH	Serial Clock High Time	—	1/(2×FCLK)	—	ns	—
QSPI_5	TSCKL	Serial Clock Low Time	—	1/(2×FCLK)	—	ns	—
QSPI_7	TSCKR	Serial Clock Rise Time	—	—	DI27	ns	See DI27 parameter in the I/O Pin AC/DC Electrical Specifications table in the I/O Pin AC/DC Electrical Specifications from Related Links
QSPI_9	TSCKF	Serial Clock Fall Time	—	—	DI25	ns	See DI25 parameter in the I/O Pin AC/DC Electrical Specifications table in the I/O Pin AC/DC Electrical Specifications from Related Links
QSPI_11	TCSS	CS Active Setup Time	5	—	—	ns	Configurable using BAUD.DLYBS register minimum time at BAUD.DLYBS = 0 and Max QSPI peripheral Clock Frequency
QSPI_13	TCSH	CS Active Hold Time	5	—	—	ns	Configurable using CTRLB.DLYBCT register minimum time at CTRLB.DLYBCT = 0 and maximum QSPI peripheral Clock Frequency
QSPI_19	TDIS	Data In Setup Time	2.8	—	—	ns	Host SDR mode
			2.8	—	—	ns	Host DDR mode, SCLK Rise
			3.67	—	—	ns	Host DDR mode, SCLK Fall
QSPI_21	TDIH	Data In Hold Time	0.794	—	—	ns	Host SDR mode
			0.428	—	—	ns	Host DDR mode, SCLK Rise
			0.793	—	—	ns	Host DDR mode, SCLK Fall
QSPI_23	TDOH	Data Out Hold	0.376	—	—	ns	Host SDR mode
QSPI_25	TDOV	Data Out Valid	—	—	8.025	ns	Host SDR mode
Note: Assumes V_{DDIOx (minimum)} and 30 pF external load on all QSPI pins unless otherwise noted. These parameters are characterized, but not tested in manufacturing.

Table 49-33. QSPI Maximum Frequency Example
AC Characteristics			Standard Operating Conditions: V_DD33 = V_DDIO = AV_DD = 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40°C ≤ T_A ≤ +125°C for Extended Temp
QSPI Mode	CLK_QSPI2X_AHB	CLK_QSPI_AHB	Maximum fCPU	Maximum QSPI Serial Clock Frequency⁽²⁾	Conditions
SDR	x	128 MHz	128 MHz	32 MHz	BAUD.BAUD[7:0] must be greater than two to ensure QSPI clock frequency. DIRECT Pin Configuration
SDR	x	128 MHz	128 MHz	16 MHz	BAUD.BAUD[7:0] must be greater than six to ensure QSPI clock frequency. Remappable Pin Configuration
DDR	128	64 MHz	64 MHz	16 MHz	BAUD.BAUD[7:0] must be greater than six to ensure QSPI clock frequency. DIRECT Pin Configuration
DDR	128	64 MHz	64 MHz	8 MHz	BAUD.BAUD[7:0] must be greater than 14 to ensure QSPI clock frequency. Remappable Pin Configuration
Note: The examples do not supersede the electrical specifications. For more details, refer to the QSPI Module Electrical Specifications. For maximum QSPI Serial Clock Frequency (FCLK) in SDR and DDR modes, refer to the QSPI_1 parameter from the QSPI Module Electrical Specifications table.