49.13 External XTAL and Clock (POSC) AC Electrical Specifications

Table 49-14. External XTAL and Clock (POSC) AC Electrical Specifications
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ.⁽¹⁾	Max.	Units	Conditions
XOSC_1	FOSC_XOSC	XOSC Crystal Frequency	—	16	—	MHz	XIN, XOUT Primary Oscillator ± 40 ppm
XOSC_1A	TOSC	TOSC = 1/FOSC_XOSC	—	62.5	—	ns	See parameter XOSC1 for FOSC_XOSC value
XOSC_2	XOSC_ST ⁽²⁾	XOSC Crystal Start-up Time	—	1.25	2.5	ms	Crystal stabilization time+Oscillator Ready
XOSC_3	C_XIN	XOSC X_IN parasitic pin capacitance	—	0.35	—	pF	—
XOSC_5	C_XOUT	XOSC X_OUT parasitic pin capacitance	—	0.35	—	pF	—
XOSC_11	C_LOAD⁽³⁾	Crystal load capacitance FOSC = 16 MHz	—	8		pF	—
XOSC_21	ESR	Crystal Frequency FOSC = 16 MHz	—	—	100	Ω
XOSC_31	IDD_XOSC	Oscillator Current (XOSC)	—	264	750	µA	XTAL_OSC power consumption at its resonance frequency
XOSC_33	D_LEVEL	MCU Crystal Osc Power Drive Level	—	100		µW	—
XOSC_34	Gm⁽⁴⁾	XOSC Transconductance	14	—	—	mA/V	—
Note: Typical value tested but not characterized. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitics that are outside the scope of this specification. If this is a major concern, the customer must characterize this based on their design choices. The test conditions for the crystal load capacitor calculation are as follows: Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (in other words, PCB STD TRACE W = 0.175 mm, H = 36 μm, T = 113 μm). Xtal PCB capacitance typical; therefore, ~= 2.5 pF for a tight PCB xtal layout For CXIN and CXOUT within 4 pF of each other, assume CXTAL_EFF = ((CXIN+CXOUT)/2). Note: Averaging CXIN and CXOUT will affect the final calculated CLOAD value by less than 0.25 pF. Equation 49-1. Equation 1: $M F G C L O A D S p e c = {([C X I N + C 1] \times [C X O U T + C 2]) / [C X I N + C 1 + C 2 + C X O U T]} + e s t i m a t e d o s c i l l a t o r P C B s t r a y c a p a c i t a n c e$ Assuming C1 = C2 and CXin ~= CXout, the formula can be further simplified and restated to solve for C1 and C2 by: Equation 49-2. Equation 2 (In other words: Simplified Equation 1) $C 1 = C 2 = ((2 \times M F G C L O A D S p e c) - C X T A L_E F F - (2 \times P C B c a p a c i t a n c e))$ Example: XTAL Mfg CLOAD Data Sheet Specification = 12 pF PCB XTAL trace Capacitance = 2.5 pF CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF; therefore, CXTAL_EFF = ((CXIN+CXOUT)/2) CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF C1 = C2 = ((2 × MFG Cload spec) – CXTAL_EFF – (2 × PCB capacitance)) C1 = C2 = (24 - 5.5 – (2 × 2.5)) C1 = C2 = 13.5 pF (Always rounded down) C1 = C2 = 13 pF (in other words, for hypothetical example crystal external load capacitors) User C1 = C2 = 13 pF CLOAD (maximum) specification For guaranteed crystal start-up, XOSC Auto Gain disabled: MCU Gm (spec) / Gm_crit >= 5; MCU Gm at specified XOSC Gain level Gm_crit = 4×ESR(max)×(2π×F)2×(C0+CL)2; Calculated Crystal Gm F = Crystal Freq, C0 = Crystal Shunt Capacitance , CL = C1 = C2 = Calculated CLOAD of circuit

Figure 49-16. External XTAL and Clock Diagram