12.6.15 PWM Generator x I/O Control Register Low
| Name: | PGxIOCONL |
| Offset: | 0x330, 0x366, 0x39C, 0x3D2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLMOD | SWAP | OVRENH | OVRENL | OVRDAT[1:0] | OSYNC[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTDAT[1:0] | CLDAT[1:0] | FFDAT[1:0] | DBDAT[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – CLMOD Current-Limit Mode Select bit
| Value | Description |
|---|---|
1 |
If the PCI current limit is active, then the PWMxH and PWMxL output signals are inverted (bit flipping), and the CLDAT[1:0] bits are not used. |
0 |
If the PCI current limit is active, then the CLDAT[1:0] bits define the PWM output levels. |
Bit 14 – SWAP Swap PWM Signals to PWMxH and PWMxL Device Pins bit
| Value | Description |
|---|---|
1 |
PWMxH signal is connected to the PWMxL pin, and the PWMxL signal is connected to the PWMxH pin. |
0 |
PWMxH/L signals are mapped to their respective pins. |
Bit 13 – OVRENH User Override Enable for PWMxH Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT1 provides data for output on the PWMxH pin. |
0 |
PWM Generator provides data for the PWMxH pin. |
Bit 12 – OVRENL User Override Enable for PWMxL Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT0 provides data for output on the PWMxL pin. |
0 |
PWM Generator provides data for the PWMxL pin. |
Bits 11:10 – OVRDAT[1:0] Data for PWMxH/PWMxL Pins if Override is Enabled bits
If OVERENH = 1, then OVRDAT1 provides data for PWMxH.
If OVERENL = 1, then OVRDAT0 provides data for PWMxL.
Bits 9:8 – OSYNC[1:0] User Output Override Synchronization Control bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits occur when specified by the UPDMOD[2:0] bits in the PGxCONH register. |
01 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits occur immediately (as soon as possible). |
00 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits are synchronized to the local PWM time base (next Start-of-Cycle). |
Bits 7:6 – FLTDAT[1:0] Data for PWMxH/PWMxL Pins if Fault Event is Active bits
If Fault is active, then FLTDAT1 provides data for PWMxH.
If Fault is active, then FLTDAT0 provides data for PWMxL.
Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if Current-Limit Event is Active bits
If current limit is active, then CLDAT1 provides data for PWMxH.
If current limit is active, then CLDAT0 provides data for PWMxL.
Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active bits
If feed-forward is active, then FFDAT1 provides data for PWMxH.
If feed-forward is active, then FFDAT0 provides data for PWMxL.
Bits 1:0 – DBDAT[1:0]
Data for PWMxH/PWMxL Pins if Debug Mode is Active and PTFRZ =
1 bits
If Debug mode is active and PTFRZ = 1, then DBDAT1 provides
data for PWMxH.
If Debug mode is active and PTFRZ = 1, then DBDAT0 provides
data for PWMxL.