12.6.13 PWM Generator x Control Register High

Note:
  1. The PCI-selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0] bits if the PCI Sync function is enabled.
  2. The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM Generator. If not, the source must be routed through the PCI Sync logic so that the trigger signal may be synchronized to the PWM Generator clock domain.
  3. PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within a group of four may be used to trigger another generator within the same group.

Legend: r = Reserved bit

Name: PGxCONH
Offset: 0x32C, 0x362, 0x398, 0x3CE

Bit 15141312111098 
 MDCSELMPERSELMPHSEL MSTENUPMOD[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
 ReservedTRGMOD  SOCS[3:0] 
Access rR/WR/WR/WR/WR/W 
Reset 000000 

Bit 15 – MDCSEL Master Duty Cycle Register Select bit

ValueDescription
1 PWM Generator uses the MDC register.
0 PWM Generator uses the PGxDC register.

Bit 14 – MPERSEL Master Period Register Select bit

ValueDescription
1 PWM Generator uses the MPER register.
0 PWM Generator uses the PGxPER register.

Bit 13 – MPHSEL Master Phase Register Select bit

ValueDescription
1 PWM Generator uses the MPHASE register.
0 PWM Generator uses the PGxPHASE register.

Bit 11 – MSTEN Master Update Enable bit

ValueDescription
1 PWM Generator broadcasts the software set/clear of the UPDATE status bit and EOC signal to other PWM Generators.
0

PWM Generator does not broadcast the UPDATE status bit state or EOC signal.

Bits 10:8 – UPMOD[2:0] PWM Buffer Update Mode Selection bits

ValueDescription
011

Client Immediate Update:

Updates data registers immediately, or as soon as possible, when a Master update request is received. A Master update request will be transmitted if MSTEN = 1 and UPDREQ = 1 for the requesting PWM Generator.
010

Client SOC Update:

Updates data registers at start of next cycle if a Master update request is received. A Master update request will be transmitted if MSTEN = 1 and UPDREQ = 1 for the requesting PWM Generator.
001

Immediate Update:

Updates data registers immediately, or as soon as possible, if UPDREQ = 1. The UPDATE status bit will be cleared automatically after the update occurs.
000

SOC Update:

Updates data registers at start of next PWM cycle if UPDREQ = 1. The UPDATE status bit will be cleared automatically after the update occurs.(1)

Bit 7 – Reserved  Maintain as ‘0’

Bit 6 – TRGMOD PWM Generator Trigger Mode Selection bit

ValueDescription
1

PWM Generator operates in Retriggerable mode.
0

PWM Generator operates in Single Trigger mode.

Bits 3:0 – SOCS[3:0]  Start-of-Cycle Selection bits(1,2,3)

ValueDescription
1111

TRIG bit or PCI Sync function only (no hardware trigger source is selected).
1110-0101

Reserved
0100

PWM4 trigger output selected by PGTRGSEL[2:0] (PGxEVT[2:0]).
0011

PWM3 trigger output selected by PGTRGSEL[2:0] (PGxEVT[2:0]).
0010

PWM2 trigger output selected by PGTRGSEL[2:0] (PGxEVT[2:0]).
0001

PWM1 trigger output selected by PGTRGSEL[2:0] (PGxEVT[2:0]).
0000

Local EOC – PWM Generator is self-triggered.