12.6.17 PWM Generator x Event Register Low

Note:
  1. These events are derived from the internal PWM Generator time-base comparison events.
Name: PGxEVTL
Offset: 0x334, 0x36A, 0x3A0, 0x3D6

Bit 15141312111098 
 ADTR1PS[4:0]ADTR1EN3ADTR1EN2ADTR1EN1 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
    UPDTRG[1:0]PGTRGSEL[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection bits

ValueDescription
11111

1:32

. . .
00010

1:3

00001

1:2

00000

1:1

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable bit

ValueDescription
1 PGxTRIGC register compare event is enabled as a trigger source for ADC Trigger 1.
0 PGxTRIGC register compare event is disabled as a trigger source for ADC Trigger 1.

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable bit

ValueDescription
1 PGxTRIGB register compare event is enabled as a trigger source for ADC Trigger 1.
0 PGxTRIGB register compare event is disabled as a trigger source for ADC Trigger 1.

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable bit

ValueDescription
1 PGxTRIGA register compare event is enabled as a trigger source for ADC Trigger 1.
0 PGxTRIGA register compare event is disabled as a trigger source for ADC Trigger 1.

Bits 4:3 – UPDTRG[1:0] Update Trigger Select bits

ValueDescription
11

A write to the PGxTRIGA register automatically sets the UPDATE bit.

10

A write to the PGxPHASE register automatically sets the UPDATE bit.

01

A write to the PGxDC register automatically sets the UPDATE bit.

00

User must set the UPDATE bit (PGxSTAT[4]) manually.

Bits 2:0 – PGTRGSEL[2:0]  PWM Generator Trigger Output Selection bits(1)

ValueDescription
111

Reserved

110

Reserved

101

Reserved

100

Reserved

011

PGxTRIGC compare event is the PWM Generator trigger.

010

PGxTRIGB compare event is the PWM Generator trigger.

001

PGxTRIGA compare event is the PWM Generator trigger.

000

EOC event is the PWM Generator trigger.