12.6.23 PWM Generator x Leading-Edge Blanking Register Low
Note:
- Bits[2:0] are read-only and always
remain as ‘
0’.
| Name: | PGxLEBL |
| Offset: | 0x348, 0x37E, 0x3B4, 0x3EA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LEB[12:5] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LEB[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 15:3 – LEB[12:0] Leading-Edge Blanking Period bits(1)
0.