12.6.1 PWM Clock Control Register
Note:
- A device-specific unlock sequence must be performed before this bit can be cleared.
- Changing the MCLKSEL[1:0] bits
while ON (PGxCONL[15]) =
1is not recommended.
| Name: | PCLKCON |
| Offset: | 0x300 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVSEL[1:0] | MCLKSEL[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 8 – LOCK Lock bit(1)
| Value | Description |
|---|---|
1 |
Write-protected registers and bits are locked. |
0 |
Write-protected registers and bits are unlocked. |
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection bits
| Value | Description |
|---|---|
11 |
Divide ratio is 1:16 |
10 |
Divide ratio is 1:8 |
01 |
Divide ratio is 1:4 |
00 |
Divide ratio is 1:2 |
Bits 1:0 – MCLKSEL[1:0] PWM Master Clock Selection bits(2)
| Value | Description |
|---|---|
11 |
FVCO/3 |
10 |
FPLLO |
01 |
FVCO/2 |
00 |
FOSC |