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12.6 Control Registers
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12.6.28 PWM Generator x Select PCI Register High
PWM Generator x Select PCI Register High

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12.6.28 PWM Generator x Select PCI Register High

Note:

Selects ‘0’ if selected PWM Generator is not present.

Name:	PGxSPCIH
Offset:	0x346, 0x37C, 0x3B2, 0x3E8


Bit	15	14	13	12	11	10	9	8
	BPEN	BPSEL[2:0]				ACP[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	SWPCI	SWPCIM[1:0]		LATMOD	TQPS	TQSS[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – BPEN PCI Bypass Enable bit

Value	Description
`1`	PCI function is enabled, and the local PCI logic is bypassed; the PWM Generator will be controlled by the PCI function in the PWM Generator selected by the BPSEL[2:0] bits.
`0`	PCI function is not bypassed.

Bits 14:12 – BPSEL[2:0] PCI Bypass Source Selection bits⁽¹⁾

Value	Description
`111`	PCI control is sourced from PWM Generator 8 PCI logic when BPEN = `1`.
`110`	PCI control is sourced from PWM Generator 7 PCI logic when BPEN = `1`.
`101`	PCI control is sourced from PWM Generator 6 PCI logic when BPEN = `1`.
`100`	PCI control is sourced from PWM Generator 5 PCI logic when BPEN = `1`.
`011`	PCI control is sourced from PWM Generator 4 PCI logic when BPEN = `1`.
`010`	PCI control is sourced from PWM Generator 3 PCI logic when BPEN = `1`.
`001`	PCI control is sourced from PWM Generator 2 PCI logic when BPEN = `1`.
`000`	PCI control is sourced from PWM Generator 1 PCI logic when BPEN = `1`.

Bits 10:8 – ACP[2:0] PCI Acceptance Criteria Selection bits

Value	Description
`111`	Reserved
`110`	Reserved
`101`	Latched any edge
`100`	Latched rising edge
`011`	Latched
`010`	Any edge
`001`	Rising edge
`000`	Level-sensitive

Bit 7 – SWPCI Software PCI Control bit

Value	Description
`1`	Drives a ‘`1`’ to PCI logic assigned to by the SWPCIM[1:0] control bits.
`0`	Drives a ‘`0`’ to PCI logic assigned to by the SWPCIM[1:0] control bits.

Bits 6:5 – SWPCIM[1:0] Software PCI Control Mode bits

Value	Description
`11`	Reserved
`10`	SWPCI bit is assigned to termination qualifier logic.
`01`	SWPCI bit is assigned to acceptance qualifier logic.
`00`	SWPCI bit is assigned to PCI acceptance logic.

Bit 4 – LATMOD PCI SR Latch Mode bit

Value	Description
`1`	SR latch is Reset-dominant in Latched Acceptance modes.
`0`	SR latch is Set-dominant in Latched Acceptance modes.

Bit 3 – TQPS Termination Qualifier Polarity Select bit

Value	Description
`1`	Inverted
`0`	Not inverted

Bits 2:0 – TQSS[2:0] Termination Qualifier Source Selection bits

Value	Description
`111`	SWPCI control bit only (qualifier forced to ‘`0`’).
`110`	Selects PCI Source #9
`101`	Selects PCI Source #8
`100`	Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits).
`011`	PWM Generator is triggered.
`010`	LEB is active.
`001`	Duty cycle is active (base PWM Generator signal).
`000`	No termination qualifier used (qualifier forced to ‘`1`’).

DS70005633B

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