17.3.9 List Triggers and Interrupts

Each list defines one trigger source to process all records. Depending on the mode, one trigger can start the back-to-back processing of all records in the list (scan). Or each record can be triggered separately. For indication, the TACK bit in the ITCLSxSTAT register is set during the trigger processing.

The record is assumed “processed” if all accumulations for the record are done as defined by ACCCNT[3:0] bits when ACCEN bit = 1 in the ITCLSxSEQ register.

The ITC module has two types of interrupts: for each list and a common interrupt. The common interrupt is generated when any list interrupt occurs. Depending on the mode, the interrupts can be disabled, generated per each record or generated when the entire list has been processed.

In addition, the interrupts can be generated by the acquisition sequencer command when the INT bit is set.

The status interrupt flags are available for each list. The INT sticky flags are set in ITCLSxSTAT registers when list interrupts occur. The flags are set by hardware and should be cleared by software. These INT bits are mirrored in the ITCSTAT register. The list interrupt flag can be cleared by software in two places, ITCLSxSTAT or ITCSTAT.

The records list has several Trigger and Interrupts modes selected by MODE[2:0] bits in the ITCLSxCON register. The following options are available:

• MODE[2:0] = 7: One trigger executes back-to-back processing for all records. The list interrupt is generated after the last list record is processed if at least one record result matches the comparator criteria.
• MODE[2:0] = 6: One trigger executes back-to-back processing for all records. The list interrupts are generated for records every time when the record result matches the comparator criteria.
• MODE[2:0] = 5: One trigger executes back-to-back processing for all records. The list interrupt is generated after the last record is processed.
• MODE[2:0] = 4: One trigger executes back-to-back processing for all records. The list interrupts are not generated.
• MODE[2:0] = 2: One record is processed per one trigger. The list interrupt is generated after the last record is processed.
• MODE[2:0] = 1: One record is processed per one trigger. The list interrupt is generated after each record is processed.
• MODE[2:0] = 0: One record is processed per one trigger. The interrupts are not generated by the list.

The trigger source for the list is defined in SSRC[4:0] bits of the ITCLSxCON register. The list triggering is enabled by setting the TRGEN bit (ITCLSxCON[15]). The Trigger Enable bits are mirrored in the ITCCON2 register. The list trigger can be enabled in two places, ITCLSxCON or ITCCON2.

The ITC module has an internal timer to generate periodical triggers. The timer period is set by TMRPR[15:0] bits in the ITCCON2 register, and the timer is clocked from ITC clock (ADC 5 clock). The trigger option for the internal timer is SSRC[6:0] bits = 7.