17.3.17 Math Sequencer Commands

The math post-processing sequence is called by an acquisition sequence. The internal structure of the math hardware is shown in Figure 17-9.

Figure 17-9. Math Sequence Harware Block Diagram

The sequence is finished when the END bit is set.

The arithmetic module has two inputs: AIN and BIN. For input A (AIN), the following sources can be selected:

  • 0 = Zero
  • 1 = Accumulator A
  • 2 = Reserved
  • 3 = ADC5 Conversion Result

For input B (BIN), the following sources can be selected:

  • 0 = ITCRESx register
  • 1 = Accumulator B
  • 2 = Reserved
  • 3 = ADC5 Conversion Result

The math sequence command executes a math operation as specified by F[1:0] bits. The following options are available:

  • 0 = data from A input is copied to the math result.
  • 1 = data from B input is copied to the math result .
  • 2 = the math result is a sum of B and A inputs.
  • 3 = the math result is a difference between of B and A inputs.

The output of the math operation is stored in the ITCRESx register if it is defined by WM[1:0] bits of the ITCLSxCON register or by WM[1:0] bits in the SMATHCMDx command when the WMOV bit is set. Also, the math result can be latched into two accumulators when ACCA and/or ACCB bits are set.

Both accumulators A and B are reset to zero by hardware before the record’s processing is started.