17.3.8 Result
When each record is processed by the math sequencer. The math sequencer result can be stored as
defined by Write mode bits WM[1:0] in the ITCLSxCON register. Also, ITCLSxCON WM[1:0]
bits can be overwritten/replaced with other SnMATHCMDx WM[1:0] settings in the math
sequencer command. These bits in the math command overwrite the list register settings
WM[1:0], only when WMOV bit = 1
in the math command. The following
write result options are available:
- WM[1:0] =
0
means “always write”. - WM[1:0] =
1
means that the math result is stored only when comparator event is detected. - WM[1:0] =
2
means “never write”. - WM[1:0] =
3
means that the math result is stored only when comparator event is not detected.
For each record, each math sequencer command stores a result in the corresponding ITCRESx
register as defined by WM[1:0] bits. The data processed by the math sequencer can be in
unsigned or signed formats. The format is selected by SIGN bit in ITCCON1 register. SIGN
bit = 0
means unsigned, and SIGN bit = 1
means sign
format. The CVD algorithm accumulates the difference between Sample A and B. In this
case for CVD, the SIGN bit always must be set.
All data in the math sequencer are 24-bit in size. Bit 23 is a sign bit. When the math sequencer signed result is stored into 32-bit ITCRESx register, the sign bit is extended automatically.