17.3.16 Acquisition Sequencer Commands
The acquisition sequence is executed each time the record is triggered.
The sequence is finished when the END bit is set.
The command can delay the execution as specified in LOOP[3:0] bits.
Each acquisition sequence must call the math sequence. It is done if the MSTART bit is set in the command. One acquisition sequence can run two different math sequences. The SECOND bit selects the math sequence that should be called (first or second).
The CVD capacitors array is controlled by DISCHRG (discharge to VSS), CHRG (charge to VDD) and BAL (connect to CVDANx pin) bits.
When the BAL bit is set to balance the charge between the CVD capacitor and the CVDANx sensor,
the four list timers in the ITCLSxTMR register can be used to provide a settle delay
required. The timer to wait is selected by LOOP[3:0] bits. In addition, the option
LOOP[3:0] = 3 allows using SAMC[4:0] bits in the ITCLSxCON as a
timer.
The CONV bit starts a conversion of an analog level on the CVD capacitor. The command can wait
for the end of the conversion if LOOP[3:0] bits = 4.
The CVDANx pin is controlled by PC0[1:0] bits. The following options are available:
0– CVDANx pin is controlled by the corresponding TRIS and LAT bits.1– CVDANx pin is driven to a low level.2– CVDANx pin is driven to a high level.3– CVDANx pin is tri-stated.
In addition, the acquisition command can control up to three CVDTXx pins. These pins can be used to implement the mutual capacitance, low impedance signal or active guards.
The PCA[1:0] bits control CVDTXx pins assigned in ITCTXA register.
The PCB[1:0] bits control CVDTXx pins assigned in ITCTXB register.
The PCC[1:0] bits control CVDTXx pins assigned in ITCTXC register.
The available options are the same as CVDANx pin control:
0– CVDTXx pin is controlled by the corresponding TRIS and LAT bits.1– CVDTXx pin is driven to a low level.2– CVDTXx pin is driven to a high level.3– CVDTXx pin is tri-stated.