17.3.7 Balance, Conversion and Sequencers Timing

The ITC, including the acquisition and math sequencers, runs from ADC5 TAD clock. The typical ADC 5 clock frequency is 80MHz. So, each sequencer command takes 12.5nS.

The CVD charge balance time is controlled in the acquisition commands. Also, the SAMC[4:0] bits of the ITCSLxCON register can be used to define the balance delay in the ADC 5 TAD steps (12.5nS typical). The balance time is started using the BAL bit in the acquisition sequence command. The acquisition sequencer can wait until the time defined by SAMC[4:0] bits is elapsed when LOOP[3:0] bits = 3 in the acquisition sequencer command.

The conversion of an analog level on the internal CVD capacitors array is done by ADC 5. The ADC 5 conversion takes two TAD cycles (or 25nS typical). The conversion is triggered by CONV bit in the acquisition sequence command. The acquisition sequencer can wait until the conversion ends when LOOP[3:0] bits = 4 in the acquisition sequencer command.