17.3.3 CVD Active Guards Pins

To reduce the base capacitance of the CVDANx sensor and increase the sensitivity, the active guards’ traces around the sensor following CVDANx voltage (CVD waveform) can be used. The idle neighbor pins to a CVDANx pin (CVDANx-1 and CVDANx+1) can function as active guards when enabled by GRDA[1:0] and GRDB[1:0] bits in the record register ITCRECx. For the CVDANx pin assigned by PIN[6:0] bits, the GRDA[1:0] bits and GRDB[1:0] bits map the guard signal to CVDANx-1 and CVDANx+1 pins. The following options are available:

• Active guards are not used/disabled when GRDA[1:0] and GRDB[1:0] = 0 or 3.
• PCA[1:0] and/or PCB[1:0] bits in the acquisition commands will control CVDANx-1 when GRDA[1:0] = 1 and/or GRDB[1:0] = 1.
• PCA[1:0] and/or PCB[1:0] bits in the acquisition commands will control CVDANx+1 when GRDA[1:0] = 2 and/or GRDB[1:0] = 2.