17.3.12 CVD Capacitors Array

The ITC has an internal CVD capacitor with a varied capacitance (2pF-18pF) to implement the CVD measurement sequence. The CVD capacitor value can be adjusted using CVDCAP[3:0] bits in the ITCLSxSEQ register with 1pF step. To achieve the maximum CVD sensitivity, the internal CVD capacitance should be as close as possible to the sensor’s capacitance. The internal CVD capacitor is enabled by the CVDEN bit in the ITCCON1 register. The CVDEN bit must always be set during ITC initialization for the CVD operation. The CVD capacitor can be connected to ground (discharged) when the DISCHRG bit is set in the acquisition sequence command, and the CVD capacitor can be connected to power (charged) when the CHRG bit is set in the acquisition sequence command. The CVD capacitor is connected to the CVDANx pin (sensor) to balance the charge when the BAL bit is set in the acquisition sequence command.