5.3.10 PWB ECC RAM Status Register
Legend: R = Readable bit; W = Writable bit; C = Clearable bit; HS = Hardware
Settable bit
Note:
- This bit determines whether the PWBxECCEADDR, PWBxECCEDATA, PWBxECCVAL and PWBxECCSYND registers display information related to SEC or DED error events.
| Name: | PWBXECCSTAT, PWBYECCSTAT |
| Offset: | 0x35A4, 0x35E4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ESEL | PWBNE | ||||||||
| Access | R/W | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECO | SEC | DEDO | DED | ||||||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 12 – ESEL Error Reporting Select bit(1)
| Value | Description |
|---|---|
1 |
Show SEC error event information. |
0 |
Show DED error event information. |
Bit 8 – PWBNE Posted Write Buffer Not Empty Status bit
| Value | Description |
|---|---|
1 |
PWB has to perform at least one read or data merge or write operation, i.e., it is not empty. |
0 |
PWB is empty, all data committed to RAM. |
Bit 5 – SECO Single Error Correction Event Overflow Status bit
| Value | Description |
|---|---|
1 |
SEC event not captured due to overflow. |
0 |
No SEC event overflow detected. |
Bit 4 – SEC Single Error Correction Status bit
| Value | Description |
|---|---|
1 |
Single-bit error detected. |
0 |
Single-bit error not detected. |
Bit 1 – DEDO Double Error Detection Event Overflow Status bit
| Value | Description |
|---|---|
1 |
DED event not captured due to overflow. |
0 |
No DED event overflow detected. |
Bit 0 – DED Double Error Detection Indicator Status bit
| Value | Description |
|---|---|
1 |
Double-bit error detected. |
0 |
Double-bit error not detected. |