5.3.5 RAM ECC Error Address Register

Legend: R = Readable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit

Name:	RAMXECCEADDR, RAMYECCADDR
Offset:	0x3590, 0x35D0


Bit	31	30	29	28	27	26	25	24
	ECCEADDR[31:24]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ECCEADDR[23:16]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ECCEADDR[15:8]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ECCEADDR[7:0]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ECCEADDR[31:0] ECC RAM Read Data Address bits

These bits represent the faulty memory location when Single bit (SEC) or Double bit (DED) ECC errors occur. The values of these register bits represent the relative address from the start address of the X or Y data spaces, depending on the instance of this register. To determine the corresponding system bus address, the start address should be added to this relative address.