5.3.9 PWB ECC RAM Control Register

Note:
  1. This bit can be set by software but not cleared. It is cleared by any device Reset.

Legend: R = Readable bit; W = Writable bit; S = Settable bit

Name: PWBXECCCON, PWBYECCCON
Offset: 0x35A0, 0x35E0

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ON        
Access R/S 
Reset 0 
Bit 76543210 
        FLTINJ 
Access R/W 
Reset 0 

Bit 15 – ON  Enable ECC functionality bit(1)

By default, ECC is disabled at a device Reset. It is the software responsibility to initialize the RAM locations with valid data, then set this bit to “1”.
ValueDescription
1 ECC is enabled.
0 ECC is disabled.

Bit 0 – FLTINJ Fault Injection Enable bit

ValueDescription
1 Fault injection is enabled when the content of the RAM address matches PWBECCXFADDR[23:2].
0 Fault injection is disabled.