Legend: R = Readable bit; HC = Hardware Clearable bit; HS = Hardware Settable
bit
Name:
PWBXECCEDATA, PWBYECCEDATA
Offset:
0x35B4,
0x35F4
Bit
31
30
29
28
27
26
25
24
ECCEDATA[31:24]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ECCEDATA[23:16]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ECCEDATA[15:8]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ECCEDATA[7:0]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – ECCEDATA[31:0] RAM Read Error Data bits
These bits represent
the value stored in the faulty memory location when Single or Double bit ECC errors
occur.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
