3.3.3 Addressing Modes
The CPU supports up to eight addressing modes as shown in Table 3-1
|
Function (Source, ppp) |
Function (Destination, qqq) | Description |
|---|---|---|
| EA = [Ws + Wb] | EA = [Wd + Wb] | Indirect with (signed) register offset |
| EA = SR | EA = SR | Status register direct |
| EA = [Ws+=1] | EA = [Wd+=1] | Register indirect pre-incremented |
| EA = [Ws-=1] | EA = [Wd-=1] | Register indirect pre-decremented |
| EA = [Ws]+= 1 | EA = [Wd]+= 1 | Register indirect post-incremented |
| EA = [Ws]-= 1 | EA = [Wd]-= 1 | Register indirect post-decremented |
| EA = [Ws] | EA = [Wd] | Register indirect |
| EA = Ws | EA = Wd | Register direct |
Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. For most instructions, the dsPIC33A CPU can execute all of the following functions in a single instruction cycle:
- Data memory read
- Working register (data) read
- Data memory write
- Program (instruction) memory read
As a result, three-operand instructions can be supported, allowing A + B = C operations to be executed in a single cycle.