3.3.12 DSP Engine
The DSP engine is a block of hardware that is fed data from the W register array, but contains its own specialized result registers. The DSP engine is driven from the same instruction decoder that directs the MCU ALU. In addition, all operand Extended Addresses (EAs) are generated in the W register array. Concurrent operation with MCU instruction flow is not possible, though both the MCU ALU and DSP engine resources can be shared by all instructions in the instruction set.
The DSP engine consists of the following components:
- High-speed, 33-bit by 33-bit multiplier
- Barrel shifter
- 72-bit adder/subtractor
- Two target Accumulator registers
- Rounding logic with selectable modes
- Saturation logic with selectable modes
Data input to the DSP engine is derived from one of the following sources:
- Directly from the W array for dual source operand DSP instructions; Data values fetched via the X and Y memory data buses.
- From the X memory data bus for all other DSP instructions
Data output from the DSP engine is written to one of the following destinations:
- The target accumulator, as defined by the DSP instruction being executed
- The X memory data bus to any location in the data memory address space
The DSP engine can perform inherent accumulator-to-accumulator operations that require no additional data.
The MCU shift and multiply instructions use the DSP engine hardware to obtain their results. The X memory data bus is used for data reads and writes in these operations.
Figure 3-9 illustrates a block diagram of the DSP engine.