3.3.5 DSP Engine and Instructions

The DSP engine features

• A high-speed, 33-bit by 33-bit multiplier
• A 72-bit ALU
• Two 72-bit saturating accumulators
• A 72-bit bidirectional barrel shifter, capable of shifting a 40-bit value up to 32 bits right or up to 32 bits left, in a single cycle

The DSP instructions operate seamlessly with all other instructions and are designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers. This requires that the data space be split for these instructions and linear for all others.