3.3.17 MAC Instructions
The dual source operand DSP instructions (ED,EDAC, MAC, MPY, MPYN, SQR, SQRAC, MSC, SQRSC and SQRN), also referred to as
MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively manipulate the data pointers through
register indirect tables.
These instructions support various addressing modes for X and Y data bus, where W-registers accessing these data buses may be any W-reg (except W15) for either X or Y address space accesses. Pre or post-modification values are scaled based upon instruction operand width. The MAC-class instruction also supports the ability to write the contents of the accumulator that is not being used as the instruction result destination to a memory or W-register as defined by the instruction with a restricted set of addressing modes. This is referred to as the Accumulator Write Back (AWB).
AWB is only intended for use when the DSP engine is operating in Fractional Data mode. It can only write the MS portion of the target accumulator fractional value.
MAC-class instructions are no longer tied to operand reads of X and Y address space. Operands may both be sourced from X-space, resulting in reading the operand data sequentially rather than concurrently. This will add an additional RAM data fetch delay (typically one cycle) to all such instructions.