3.3.13 Divide Support
The dsPIC33A CPU supports the following types of division operations.
- DIVF.SD: 16/16 signed fractional divide
- DIVF.SD: 32/16 signed fractional divide
- DIVF.SD: 32/32 signed fractional divide
- DIV.SD: 32/32 signed divide
- DIV.UD: 32/32 unsigned divide
- DIV.SD: 32/16 signed divide
- DIV.UD: 32/16 unsigned divide
- DIV.SW: 16/16 signed divide
- DIV.UW: 16/16 unsigned divide
The quotient for all divide instructions can placed in any Working register, Wm. The remainder is placed in W(m+1). The 32/16-bit divisor can be located in any W register. A 32/16-bit dividend can be located in any W register. The integer 16/16 divide instructions will either zero or sign extend the least significant dividend word into the most significant dividend word during the first iteration to create a 32-bit dividend.
All 16-bit/16-bit and 32-bit/16-bit divide instructions are iterative operations and must be executed six times within a REPEAT loop. All 32-bit/32-bit divide instructions are iterative operations and must be executed 10 times within a REPEAT loop.
The developer is responsible for programming the REPEAT instruction. A complete divide operation takes seven or 11 instruction cycles to execute.
The divide flow is interruptible, just like any other REPEAT loop. All data is restored into the respective data registers after each iteration of the loop, so the user application is responsible for saving the appropriate W registers in the ISR. Although they are important to the divide hardware, the intermediate values in the W registers have no meaning to the user application. The divide instructions must be executed seven or 11 times in a REPEAT loop to produce a meaningful result.
A divide-by-zero error generates a math error trap. This condition is indicated by the Arithmetic Error Status (DIV0ERR) bit (INTCON4[6] in the interrupt controller).