3.3.16 Data Space Address Generation Units (AGUs)

dsPIC33AK512MPS512 family devices contain three independent Address Generator Units (AGUs). The X RAGU and X WAGU support byte (.b), word (.w) and long word (.l)-sized data space reads and writes for MCU instructions, and word or long word reads and writes for DSP instructions. The Y AGU supports word and long word-sized data reads for the DSP MAC-class of instructions only. The AGUs are each capable of supporting two types of data addressing.

In addition, the X WAGU can support Bit-Reversed Addressing.

Linear and Modulo Data Addressing modes can be applied to any address within the unified address space. Although Bit-Reversed Addressing will work with any EA calculation, by definition, it is only applicable to data space.

Data space memory is organized as 32-bit words; all Effective Addresses (EAs) point to bytes. Instructions can thus access any byte, aligned word (data words at an even byte address) or aligned long word (data words at an even 32-bit word address).

Misaligned accesses are not supported, and if attempted, they will initiate an address error trap. The least significant two bits of the EA are used to determine the byte or upper/lower 16-bit word access. EA[0] will always be 1’b0 for word accesses, and EA[1:0] will always be 2’b00 for long word accesses.

SFRs and RAM support byte, word and double-word read or write operations.

When executing instructions that require just one source operand to be fetched from (and one result to be written back to) data space, the X RAGU and X WAGU are used to calculate the EAs of the source and destination, respectively. The AGUs can generate an address to point to anywhere in the 16 Mbyte address space. They support all MCU addressing modes and Modulo Addressing for low overhead circular buffers. The X WAGU also supports Bit-Reversed Addressing to facilitate FFT data reorganization.

When executing instructions which require two source operands to be concurrently fetched (i.e., the MAC class of DSP instructions), both the X RAGU and Y AGU are used simultaneously.

The dsPIC33AK512MPS512 device family contains an X AGU and a Y AGU for generating data memory addresses. Both X and Y AGUs can generate any EA within the available data memory range. However, EAs that are outside of the physical memory provided return all zeros for data reads and writes to those locations and, therefore, have no effect. Furthermore, an address error trap will be generated. For more information on address error traps, refer to Interrupt Controller.