10.4.1 Interrupt Control Register 1
Note:
- The user is responsible for clearing this bit by writing a zero to it.
| Name: | INTCON1 |
| Offset: | 0x70 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NSTDIS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GIE | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STKERR | ADDRERR | BADOPERR | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 31 – NSTDIS Interrupt Nesting Disable bit
| Value | Description |
|---|---|
1 |
Interrupt nesting is disabled. |
0 |
Interrupt nesting is enabled. |
Bit 15 – GIE Global Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupts are enabled (assuming associated IE bits are enabled). |
0 |
Interrupts are disabled (traps are still enabled). |
Bit 4 – STKERR Stack Error Trap Status bit(1)
| Value | Description |
|---|---|
1 |
Stack Error Trap has occurred. |
0 |
Stack Error Trap has not occurred. |
Bit 3 – ADDRERR Address Error Trap Status bit(1)
| Value | Description |
|---|---|
1 |
Address Error Trap has occurred. |
0 |
Address Error Trap has not occurred. |
Bit 2 – BADOPERR Illegal Opcode Error Trap Status bit(1)
| Value | Description |
|---|---|
1 |
Illegal Opcode Error Trap has occurred. |
0 |
Illegal Opcode Error Trap has not occurred. |