10.4.6 Interrupt Control and Status Register
Note:
- During Debug mode, the ICD can force the interrupts to be disabled. This allows the user code to progress when single stepping, even when there are interrupts pending.
- The bit fields in the INTTREG register correspond to the value of vector number, interrupt level and IRQ request flag, when an interrupt is presented to the CPU.
| Name: | INTTREG |
| Offset: | 0x84 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IRQCPU | VHOLD | ||||||||
| Access | R | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ILR[3:0] | VECNUM[8] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VECNUM[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 23 – IRQCPU Interrupt Request from Interrupt Controller to CPU bit(1)
Bit 21 – VHOLD Vector Number Capture Enable bit
| Value | Description |
|---|---|
1 |
VECNUM[8:0] bits read current value of vector number encoding tree (i.e., highest priority pending interrupt). |
0 |
Vector number latched into VECNUM[8:0] at Interrupt Acknowledge and retained until next IACK. |