10.4.3 Interrupt Control Register 3
| Name: | INTCON3 |
| Offset: | 0x78 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPUBET | DMABET | YRAMBET | XRAMBET | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CPUBET Bus Error Trap Status bit 3 (CPU Inst Data bus error)
| Value | Description |
|---|---|
1 |
Bus Error trap 1 has occurred. |
0 |
Bus Error trap 1 has not occurred. |
Bit 2 – DMABET Bus Error Trap Status bit 2 (DMA bus error)
| Value | Description |
|---|---|
1 |
Bus Error trap 1 has occurred. |
0 |
Bus Error trap 1 has not occurred. |
Bit 1 – YRAMBET Bus Error Trap Status bit 1 (CPU Y Data bus error)
| Value | Description |
|---|---|
1 |
Bus Error trap 1 has occurred. |
0 |
Bus Error trap 1 has not occurred. |
Bit 0 – XRAMBET Bus Error Trap Status bit 0 (CPU X Data bus error)
| Value | Description |
|---|---|
1 |
Bus Error trap 0 has occurred. |
0 |
Bus Error trap 0 has not occurred. |