10.4.46 Interrupt Priority Register 13
| Name: | IPC13 |
| Offset: | 0x124 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| U3EVTIP[2:0] | U3EIP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| U3TXIP[2:0] | U3RXIP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| U2EVTIP[2:0] | U2EIP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | |||
Bits 22:20 – U3EVTIP[2:0] UART3 Event Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 18:16 – U3EIP[2:0] UART3 Error Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 14:12 – U3TXIP[2:0] UART3 Transmit Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 10:8 – U3RXIP[2:0] UART3 Receive Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 6:4 – U2EVTIP[2:0] UART2 Event Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 2:0 – U2EIP[2:0] UART2 Error Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |